On 27.05.20 03:31, Chris Packham wrote:
From: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Measurements on actual hardware shown that the read ODT is early by 3
clocks. Adjust the calculation to avoid this.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham <judge.pack...@gmail.com>
---
Reviewed-by: Stefan Roese <s...@denx.de>
Thanks,
Stefan
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
index ce9a47fc2ce0..58ffb205072e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
@@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32
if_id)
min_read_sample = read_sample[cs_num];
}
- min_read_sample = min_read_sample - 1;
- max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
+ min_read_sample = min_read_sample + 2;
+ max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1;
if (min_read_sample >= 0xf)
min_read_sample = 0xf;
if (max_read_sample >= 0x1f)
Viele Grüße,
Stefan
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