On Sun, Jun 7, 2020 at 7:22 PM Jagan Teki <ja...@amarulasolutions.com> wrote: > > Some architecture like ARM Cortex A53, A72 would need > to invalidate dcache to sync the cache with the memory > contents before flushing the cache to memory. > > The NVME here submitting the admin command using dma_addr > to the memory without prior cache invalidation. This causing > dma_addr is pointing to an invalid location in the memory > and found the sane nvme_ctrl result.
insane? > > Below example shows the nvme disk scan result improper result > > => nvme scan > nvme_get_info_from_identify: nn = 544502629, vwc = 100, > sn = dev_0T, mn = `�\�, fr = t_part, mdts = 105 > > So, invalidating the cache before submitting the admin command > makes the dma_addr points to a valid location in the memory. > > Cc: Andre Przywara <andre.przyw...@arm.com> > Reported-by: Suniel Mahesh <su...@amarulasolutions.com> > Signed-off-by: Michael Trimarchi <mich...@amarulasolutions.com> > Signed-off-by: Jagan Teki <ja...@amarulasolutions.com> > Tested-by: Suniel Mahesh <su...@amarulasolutions.com> > --- > drivers/nvme/nvme.c | 3 +++ > 1 file changed, 3 insertions(+) > Reviewed-by: Bin Meng <bmeng...@gmail.com>