> -----Original Message----- > From: Marek Vasut <[email protected]> > Sent: Tuesday, June 9, 2020 5:53 PM > To: Tan, Ley Foon <[email protected]>; [email protected] > Cc: Ley Foon Tan <[email protected]>; See, Chin Liang > <[email protected]>; Simon Goldschmidt > <[email protected]>; Ang, Chee Hong > <[email protected]> > Subject: Re: [PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling- > time-ns > > On 6/9/20 8:33 AM, Tan, Ley Foon wrote: > [...] > >>> Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing > >>> calculation") change the hcnt and lcnt timing calculation. > >>> > >>> After this new timing calculation, hcnt will have negative value > >>> with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts. > >> Shouldn't either the driver or the calculation be fixed instead ? > > The original timing calculation in driver doesn't take fall time or rise > > time > into calculation. > > The new i2c timing calculation is based on calculation from Designware i2c > databook. So, I don't think need fix in driver. > > Then just mention it in the commit message that it's from the databook > please. Okay.
Regards Ley Foon
