po 18. 5. 2020 v 10:21 odesÃlatel Michal Simek <[email protected]> napsal: > > From: Ashok Reddy Soma <[email protected]> > > Remove below config options and convert them to macros. They have never > been configured to different values than default one. And also it makes > sense to reduce the config_whitelist. > CONFIG_SYS_ZYNQ_SPI_WAIT > CONFIG_SYS_ZYNQ_QSPI_WAIT > CONFIG_XILINX_SPI_IDLE_VAL > > Signed-off-by: Ashok Reddy Soma <[email protected]> > Signed-off-by: Michal Simek <[email protected]> > --- > > drivers/spi/xilinx_spi.c | 6 ++---- > drivers/spi/zynq_qspi.c | 6 ++---- > drivers/spi/zynq_spi.c | 6 ++---- > scripts/config_whitelist.txt | 3 --- > 4 files changed, 6 insertions(+), 15 deletions(-) > > diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c > index 2b5f2cf54838..a586b41c5b92 100644 > --- a/drivers/spi/xilinx_spi.c > +++ b/drivers/spi/xilinx_spi.c > @@ -74,9 +74,7 @@ > SPICR_SPE) > #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS) > > -#ifndef CONFIG_XILINX_SPI_IDLE_VAL > -#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) > -#endif > +#define XILINX_SPI_IDLE_VAL GENMASK(7, 0) > > #define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */ > > @@ -174,7 +172,7 @@ static u32 xilinx_spi_fill_txfifo(struct udevice *bus, > const u8 *txp, > > while (txbytes && !(readl(®s->spisr) & SPISR_TX_FULL) && > i < priv->fifo_depth) { > - d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; > + d = txp ? *txp++ : XILINX_SPI_IDLE_VAL; > debug("spi_xfer: tx:%x ", d); > /* write out and wait for processing (receive data) */ > writel(d & SPIDTR_8BIT_MASK, ®s->spidtr); > diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c > index 9ad1927a5d51..164746a0df85 100644 > --- a/drivers/spi/zynq_qspi.c > +++ b/drivers/spi/zynq_qspi.c > @@ -45,9 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; > #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */ > > #define ZYNQ_QSPI_FIFO_DEPTH 63 > -#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT > -#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ > -#endif > +#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */ > > /* zynq qspi register set */ > struct zynq_qspi_regs { > @@ -348,7 +346,7 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv) > do { > status = readl(®s->isr); > } while ((status == 0) && > - (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT)); > + (get_timer(timeout) < ZYNQ_QSPI_WAIT)); > > if (status == 0) { > printf("zynq_qspi_irq_poll: Timeout!\n"); > diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c > index 0b2b2f481037..ea24df278319 100644 > --- a/drivers/spi/zynq_spi.c > +++ b/drivers/spi/zynq_spi.c > @@ -33,9 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; > #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */ > > #define ZYNQ_SPI_FIFO_DEPTH 128 > -#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT > -#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ > -#endif > +#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */ > > /* zynq spi register set */ > struct zynq_spi_regs { > @@ -248,7 +246,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned > int bitlen, > ts = get_timer(0); > status = readl(®s->isr); > while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { > - if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) { > + if (get_timer(ts) > ZYNQ_SPI_WAIT) { > printf("spi_xfer: Timeout! TX FIFO not > full\n"); > return -1; > } > diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt > index 253c46159b6b..2be1022e3af8 100644 > --- a/scripts/config_whitelist.txt > +++ b/scripts/config_whitelist.txt > @@ -4015,8 +4015,6 @@ CONFIG_SYS_XHCI_USB1_ADDR > CONFIG_SYS_XHCI_USB2_ADDR > CONFIG_SYS_XHCI_USB3_ADDR > CONFIG_SYS_XIMG_LEN > -CONFIG_SYS_ZYNQ_QSPI_WAIT > -CONFIG_SYS_ZYNQ_SPI_WAIT > CONFIG_SYS_i2C_FSL > CONFIG_TAM3517_SETTINGS > CONFIG_TCA642X > @@ -4242,7 +4240,6 @@ CONFIG_X86_MRC_ADDR > CONFIG_X86_REFCODE_ADDR > CONFIG_X86_REFCODE_RUN_ADDR > CONFIG_XGI_XG22_BASE > -CONFIG_XILINX_SPI_IDLE_VAL > CONFIG_XSENGINE > CONFIG_XTFPGA > CONFIG_YAFFSFS_PROVIDE_VALUES > -- > 2.26.2 >
Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
