This patch adds the optional call to mips_mach_early_init() to start.S
at a very early stage. Its disabled per default. It can be used for
very early machine / platform specific init code.  Its called very
early and at this stage the PC is allowed to differ from the linking
address (CONFIG_TEXT_BASE) as no absolute jump has been performed until
this call.

It will be used by thje Octeon platform.

Signed-off-by: Stefan Roese <>
Reviewed-by: Daniel Schwierzeck <>

(no changes since v1)

 arch/mips/Kconfig     | 9 +++++++++
 arch/mips/cpu/start.S | 5 +++++
 2 files changed, 14 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index dd56da6dae..327fd4848a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -296,6 +296,15 @@ config MIPS_CACHE_INDEX_BASE
          Normally this is CKSEG0. If the MIPS system needs to move this block
          to some SRAM or ScratchPad RAM, adapt this option accordingly.
+       bool "Enable mach specific very early init code"
+       help
+         Use this to enable the call to mips_mach_early_init() very early
+         from start.S. This function can be used e.g. to do some very early
+         CPU / SoC intitialization or image copying. Its called very early
+         and at this stage the PC might not match the linking address
+         (CONFIG_TEXT_BASE) - no absolute jump done until this call.
        bool "Enable startup code to initialize and setup caches"
        default n if SKIP_LOWLEVEL_INIT
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 08dddbdf5f..a7190ec3b2 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -195,6 +195,11 @@ wr_done:
        /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
        mtc0    zero, CP0_COMPARE
+       bal     mips_mach_early_init
+        nop
        /* Disable caches */
        PTR_LA  t9, mips_cache_disable

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