>-----Original Message----- >From: U-Boot <[email protected]> On Behalf Of Michael Walle >Sent: Sunday, May 10, 2020 4:50 AM >To: [email protected] >Cc: Sudhanshu Gupta <[email protected]>; Harninder Rai ><[email protected]>; Rajesh Bhagat <[email protected]>; Andy >Tang <[email protected]>; Priyanka Jain <[email protected]>; >Prabhakar Kushwaha <[email protected]>; Michael Walle ><[email protected]> >Subject: [PATCH v3 2/2] board: kontron: add sl28 support > >Add basic support for the Kontron SMARC-sAL28 board. This includes just the >bare minimum to be able to bring up the board and boot linux. > >For now, the Single and Dual PHY variant is supported. Other variants will fall >back to the basic variant. > >In particular, there is no watchdog support for now. This means that you have >to disable the default watchdog, otherwise you'll end up in the recovery >bootloader. See the board README for details. > >Signed-off-by: Michael Walle <[email protected]> >--- > arch/arm/Kconfig | 10 ++ > arch/arm/dts/Makefile | 3 + > .../arm/dts/fsl-ls1028a-kontron-sl28-var3.dts | 14 ++ > .../arm/dts/fsl-ls1028a- >kontron-sl28-var4.dts | 42 ++++++ > arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 128 ++++++++++++++++++ > board/kontron/sl28/Kconfig | 18 +++ > board/kontron/sl28/MAINTAINERS | 6 + > board/kontron/sl28/Makefile | 8 ++ > board/kontron/sl28/README | 63 +++++++++ > board/kontron/sl28/common.c | 10 ++ > board/kontron/sl28/ddr.c | 98 ++++++++++++++ > board/kontron/sl28/sl28.c | 92 +++++++++++++ > board/kontron/sl28/spl.c | 9 ++ > configs/kontron_sl28_defconfig | 102 ++++++++++++++ > include/configs/kontron_sl28.h | 119 ++++++++++++++++ > 15 files changed, 722 insertions(+) > create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts > create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts > create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts > create mode 100644 board/kontron/sl28/Kconfig create mode 100644 >board/kontron/sl28/MAINTAINERS create mode 100644 >board/kontron/sl28/Makefile create mode 100644 >board/kontron/sl28/README create mode 100644 >board/kontron/sl28/common.c create mode 100644 >board/kontron/sl28/ddr.c create mode 100644 board/kontron/sl28/sl28.c >create mode 100644 board/kontron/sl28/spl.c create mode 100644 >configs/kontron_sl28_defconfig create mode 100644 >include/configs/kontron_sl28.h > >diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index >0d463088a2..9fb8d2943c 100644 >--- a/arch/arm/Kconfig >+++ b/arch/arm/Kconfig >@@ -1574,6 +1574,15 @@ config TARGET_LS1046AFRWY > development platform that supports the QorIQ LS1046A > Layerscape Architecture processor. > >+config TARGET_SL28 >+ bool "Support sl28" >+ select ARCH_LS1028A >+ select ARM64 >+ select ARMV8_MULTIENTRY >+ select SUPPORT_SPL >+ help >+ Support for Kontron SMARC-sAL28 board. >+ > config TARGET_COLIBRI_PXA270 > bool "Support colibri_pxa270" > select CPU_PXA >@@ -1904,6 +1913,7 @@ source "board/hisilicon/hikey/Kconfig" > source "board/hisilicon/hikey960/Kconfig" > source "board/hisilicon/poplar/Kconfig" > source "board/isee/igep003x/Kconfig" >+source "board/kontron/sl28/Kconfig" > source "board/phytec/pcm051/Kconfig" > source "board/silica/pengwyn/Kconfig" > source "board/spear/spear300/Kconfig" >diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index >559d3ab6a7..7050ec72eb 100644 >--- a/arch/arm/dts/Makefile >+++ b/arch/arm/dts/Makefile >@@ -379,6 +379,9 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ > fsl-ls2088a-rdb-qspi.dtb \ > fsl-ls1088a-rdb.dtb \ > fsl-ls1088a-qds.dtb \ >+ fsl-ls1028a-kontron-sl28.dtb \ >+ fsl-ls1028a-kontron-sl28-var3.dtb \ >+ fsl-ls1028a-kontron-sl28-var4.dtb \ > fsl-ls1028a-rdb.dtb \ > fsl-ls1028a-qds-duart.dtb \ > fsl-ls1028a-qds-lpuart.dtb \ >diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts >b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts >new file mode 100644 >index 0000000000..23f89eadb3 >--- /dev/null >+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts >@@ -0,0 +1,14 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+/* >+ * Kontron SMARC-sAL28 device tree source (Single PHY version) */ >+ >+/dts-v1/; >+ >+#include "fsl-ls1028a-kontron-sl28.dts" >+ >+/ { >+ u-boot,dm-pre-reloc; >+ model = "Kontron SMARC-sAL28 Board (Single PHY)"; >+ compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a"; }; >diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts >b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts >new file mode 100644 >index 0000000000..8b51cf1207 >--- /dev/null >+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts >@@ -0,0 +1,42 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+/* >+ * Kontron SMARC-sAL28 device tree source (Dual PHY version) */ >+ >+/dts-v1/; >+ >+#include "fsl-ls1028a-kontron-sl28.dts" >+#include <dt-bindings/net/qca-ar803x.h> >+ >+/ { >+ u-boot,dm-pre-reloc; >+ model = "Kontron SMARC-sAL28 Board (Dual PHY)"; >+ compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; }; >+ >+&enetc1 { >+ status = "okay"; >+ phy-mode = "rgmii-id"; >+ phy-handle = <&phy1>; >+}; >+ >+&mdio0 { >+ phy1: phy@4 { >+ reg = <4>; >+ >+ qca,clk-out-frequency = <125000000>; >+ qca,clk-out-strength = <AR803X_STRENGTH_FULL>; >+ >+ vddio-supply = <&vddh>; >+ >+ vddio: vddio-regulator { >+ regulator-name = "VDDIO"; >+ regulator-min-microvolt = <1800000>; >+ regulator-max-microvolt = <1800000>; >+ }; >+ >+ vddh: vddh-regulator { >+ regulator-name = "VDDH"; >+ }; >+ }; >+}; >diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl- >ls1028a-kontron-sl28.dts >new file mode 100644 >index 0000000000..8d4c1102c4 >--- /dev/null >+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts >@@ -0,0 +1,128 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+/* >+ * Kontron SMARC-sAL28 device tree source (base version) */ >+ >+/dts-v1/; >+ >+#include "fsl-ls1028a.dtsi" >+ >+/ { >+ u-boot,dm-pre-reloc; >+ model = "Kontron SMARC-sAL28 Board"; >+ compatible = "kontron,sl28", "fsl,ls1028a"; >+ >+ aliases { >+ serial0 = &serial0; >+ serial1 = &serial1; >+ spi0 = &fspi; >+ spi1 = &dspi2; >+ mmc0 = &esdhc0; >+ mmc1 = &esdhc1; >+ i2c0 = &i2c0; >+ i2c1 = &i2c3; >+ i2c2 = &i2c4; >+ rtc0 = &rtc; >+ ethernet0 = &enetc0; >+ ethernet1 = &enetc1; >+ ethernet2 = &enetc2; >+ ethernet3 = &enetc6; >+ }; >+ >+ chosen { >+ stdout-path = &serial0; >+ }; >+}; >+ >+&dspi2 { >+ u-boot,dm-pre-reloc; >+ status = "okay"; >+}; >+ >+&enetc0 { >+ status = "okay"; >+ phy-mode = "sgmii"; >+ phy-handle = <&phy0>; >+}; >+ >+&enetc1 { >+ status = "disabled"; >+}; >+ >+&enetc2 { >+ status = "disabled"; >+}; >+ >+&enetc6 { >+ status = "disabled"; >+}; >+ >+&esdhc0 { >+ u-boot,dm-pre-reloc; >+ status = "okay"; >+}; >+ >+&esdhc1 { >+ u-boot,dm-pre-reloc; >+ status = "okay"; >+ bus-width = <8>; >+}; >+ >+&fspi { >+ u-boot,dm-pre-reloc; >+ status = "okay"; >+ >+ flash@0 { >+ u-boot,dm-pre-reloc; >+ #address-cells = <1>; >+ #size-cells = <1>; >+ compatible = "jedec,spi-nor"; >+ m25p,fast-read; >+ spi-max-frequency = <133000000>; >+ reg = <0>; >+ spi-rx-bus-width = <2>; >+ spi-tx-bus-width = <1>; >+ }; >+}; >+ >+&i2c0 { >+ status = "okay"; >+ >+ rtc: rtc@32 { >+ compatible = "microcrystal,rv8803"; >+ reg = <0x32>; >+ }; >+}; >+ >+&i2c3 { >+ status = "okay"; >+}; >+ >+&i2c4 { >+ status = "okay"; >+}; >+ >+&mdio0 { >+ status = "okay"; >+ >+ phy0: phy@5 { >+ reg = <5>; >+ }; >+}; >+ >+&serial0 { >+ u-boot,dm-pre-reloc; >+ status = "okay"; >+}; >+ >+&sysclk { >+ u-boot,dm-pre-reloc; >+}; >+ >+&usb1 { >+ status = "okay"; >+}; >+ >+&usb2 { >+ status = "okay"; >+}; >diff --git a/board/kontron/sl28/Kconfig b/board/kontron/sl28/Kconfig new file >mode 100644 index 0000000000..cdec39be01 >--- /dev/null >+++ b/board/kontron/sl28/Kconfig >@@ -0,0 +1,18 @@ >+if TARGET_SL28 >+ >+config SYS_BOARD >+ default "sl28" >+ >+config SYS_VENDOR >+ default "kontron" >+ >+config SYS_SOC >+ default "fsl-layerscape" >+ >+config SYS_CONFIG_NAME >+ default "kontron_sl28" >+ >+config SYS_TEXT_BASE >+ default 0x96000000 >+ >+endif >diff --git a/board/kontron/sl28/MAINTAINERS >b/board/kontron/sl28/MAINTAINERS new file mode 100644 index >0000000000..047a057646 >--- /dev/null >+++ b/board/kontron/sl28/MAINTAINERS >@@ -0,0 +1,6 @@ >+Kontron SMARC-sAL28 board >+M: Michael Walle <[email protected]> >+S: Maintained >+F: board/kontron/sl28/ >+F: include/configs/kontron_sl28.h >+F: configs/kontron_sl28_defconfig >diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile new >file mode 100644 index 0000000000..0f1866c874 >--- /dev/null >+++ b/board/kontron/sl28/Makefile >@@ -0,0 +1,8 @@ >+# SPDX-License-Identifier: GPL-2.0+ >+ >+ifndef CONFIG_SPL_BUILD >+obj-y += sl28.o >+endif >+ >+obj-y += common.o ddr.o >+obj-$(CONFIG_SPL_BUILD) += spl.o >diff --git a/board/kontron/sl28/README b/board/kontron/sl28/README new >file mode 100644 index 0000000000..931563f299 >--- /dev/null >+++ b/board/kontron/sl28/README >@@ -0,0 +1,63 @@ >+Summary >+======= >+ >+The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72 >+processor module with an on-chip 6-port TSN switch and a 3D GPU. >+ >+ >+Quickstart >+========== >+ >+Compile U-Boot >+-------------- >+ >+ $ make kontron_sl28_defconfig >+ $ CROSS_COMPILE=aarch64-linux-gnu make >+ >+Copy u-boot-with-spl.bin to a TFTP server. >+ >+Install the bootloader on the board >+----------------------------------- >+ >+Please note, this bootloader doesn't support the builtin watchdog >+(yet), therefore you have to disable it, see below. Otherwise you'll >+end up in the failsafe bootloader on every reset. >+ >+ > tftp path/to/u-boot-with-spl.bin >+ > sf probe 0 >+ > sf update $fileaddr 0x210000 $filesize >+ >+The board is fully failsafe, you can't break anything. But since you've >+disabled the builtin watchdog you might have to manually enter failsafe >+mode by asserting the FORCE_RECOV# line during board reset. >+ >+Disable the builtin watchdog >+---------------------------- >+ >+ - boot into the failsafe bootloader, either by asserting the >+ FORCE_RECOV# line or if you still have the original bootloader >+ installed you can use the command "wdt dev cpld_watchdog@4a; wdt >+ expire 1" >+ - in the failsafe bootloader use the "sl28 nvm" command to disable >+ the automatic start of the builtin watchdog: >+ > sl28 nvm 0008 >+ - power-cycle the board >+ >+ >+Useful I2C tricks >+================= >+ >+The board has a board management controller which is not supported in >+u-boot (yet). But you can use the i2c command to access it: >+ >+ # reset into failsafe bootloader >+ > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42 >+ >+ # read board management controller version >+ > i2c md 4a 3.1 1 >+ >+ >+Vendor Documentation >+==================== >+ >+https://raw.githubusercontent.com/kontron/u-boot-smarc- >sal28/master/boa >+rd/kontron/sl28/README.md >diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c >new file mode 100644 index 0000000000..14704f7051 >--- /dev/null >+++ b/board/kontron/sl28/common.c >@@ -0,0 +1,10 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+ >+#include <common.h> >+#include <asm/arch-fsl-layerscape/soc.h> >+ >+int board_early_init_f(void) >+{ >+ fsl_lsch3_early_init_f(); >+ return 0; >+} >diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c new file >mode 100644 index 0000000000..110f57ac90 >--- /dev/null >+++ b/board/kontron/sl28/ddr.c >@@ -0,0 +1,98 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+ >+#include <common.h> >+#include <asm/io.h> >+#include <fsl_ddr_sdram.h> >+ >+DECLARE_GLOBAL_DATA_PTR; >+ >+#define DCFG_GPPORCR1 0x20 >+ >+#define GPPORCR1_MEM_MASK (0x7 << 5) >+#define GPPORCR1_MEM_512MB_CS0 (0x0 << 5) >+#define GPPORCR1_MEM_1GB_CS0 (0x1 << 5) >+#define GPPORCR1_MEM_2GB_CS0 (0x2 << 5) >+#define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5) >+#define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5) >+#define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5) >+#define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5) >+ >+static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = { >+ .cs[0].bnds = 0x0000007f, >+ .cs[0].config = 0x80044402, >+ .cs[1].bnds = 0x008000ff, >+ .cs[1].config = 0x80004402, >+ >+ .timing_cfg_0 = 0x9011010c, >+ .timing_cfg_3 = 0x010c1000, >+ .timing_cfg_1 = 0xbcb48c66, >+ .timing_cfg_2 = 0x0fc0d118, >+ .ddr_sdram_cfg = 0xe70c000c, >+ .ddr_sdram_cfg_2 = 0x24401111, >+ .ddr_sdram_mode = 0x00441c70, >+ .ddr_sdram_mode_3 = 0x00001c70, >+ .ddr_sdram_mode_5 = 0x00001c70, >+ .ddr_sdram_mode_7 = 0x00001c70, >+ .ddr_sdram_mode_2 = 0x00180000, >+ .ddr_sdram_mode_4 = 0x00180000, >+ .ddr_sdram_mode_6 = 0x00180000, >+ .ddr_sdram_mode_8 = 0x00180000, >+ >+ .ddr_sdram_interval = 0x0c30030c, >+ .ddr_data_init = 0xdeadbeef, >+ >+ .ddr_sdram_clk_cntl = 0x02400000, >+ >+ .timing_cfg_4 = 0x00000001, >+ .timing_cfg_5 = 0x04401400, >+ >+ .ddr_zq_cntl = 0x89080600, >+ .ddr_wrlvl_cntl = 0x8675f606, >+ .ddr_wrlvl_cntl_2 = 0x04080700, >+ .ddr_wrlvl_cntl_3 = 0x00000009, >+ >+ .ddr_cdr1 = 0x80040000, >+ .ddr_cdr2 = 0x0000bc01, >+}; >+ >+int fsl_initdram(void) >+{ >+ u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1); >+ phys_size_t dram_size; >+ >+ switch (gpporcr1 & GPPORCR1_MEM_MASK) { >+ case GPPORCR1_MEM_2GB_CS0: >+ dram_size = 0x80000000; >+ ddr_cfg_regs.cs[1].bnds = 0; >+ ddr_cfg_regs.cs[1].config = 0; >+ ddr_cfg_regs.cs[1].config_2 = 0; >+ break; >+ case GPPORCR1_MEM_4GB_CS0_1: >+ dram_size = 0x100000000ULL; >+ break; >+ case GPPORCR1_MEM_512MB_CS0: >+ dram_size = 0x20000000; >+ /* fall through for now */ >+ case GPPORCR1_MEM_1GB_CS0: >+ dram_size = 0x40000000; >+ /* fall through for now */ >+ case GPPORCR1_MEM_4GB_CS0_2: >+ dram_size = 0x100000000ULL; >+ /* fall through for now */ >+ case GPPORCR1_MEM_8GB_CS0_1: >+ case GPPORCR1_MEM_8GB_CS0_1_2_3: >+ dram_size = 0x200000000ULL; >+ /* fall through for now */ >+ default: >+ panic("Unsupported memory configuration (%08x)\n", >+ gpporcr1 & GPPORCR1_MEM_MASK); >+ break; >+ } >+ >+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) >+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); #endif >+ gd->ram_size = dram_size; >+ >+ return 0; >+} >diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c new file >mode 100644 index 0000000000..ef35541c86 >--- /dev/null >+++ b/board/kontron/sl28/sl28.c >@@ -0,0 +1,92 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+ >+#include <common.h> >+#include <malloc.h> >+#include <errno.h> >+#include <fsl_ddr.h> >+#include <asm/io.h> >+#include <fdt_support.h> >+#include <linux/libfdt.h> >+#include <env_internal.h> >+#include <asm/arch-fsl-layerscape/soc.h> #include >+<asm/arch-fsl-layerscape/fsl_icid.h> >+#include <i2c.h> >+#include <asm/arch/soc.h> >+#include <fsl_immap.h> >+#include <netdev.h> >+ >+#include <fdtdec.h> >+#include <miiphy.h> >+ >+#define DCFG_RCWSR25 0x160 >+#define GPINFO_HW_VARIANT_MASK 0xff >+ >+DECLARE_GLOBAL_DATA_PTR; >+ >+int sl28_variant(void) >+{ >+ return in_le32(DCFG_BASE + DCFG_RCWSR25) & >GPINFO_HW_VARIANT_MASK; } >+ >+int board_fit_config_name_match(const char *name) { >+ int variant = sl28_variant(); >+ >+ switch (variant) { >+ case 3: >+ return strcmp(name, "fsl-ls1028a-kontron-sl28-var3"); >+ case 4: >+ return strcmp(name, "fsl-ls1028a-kontron-sl28-var4"); >+ default: >+ return strcmp(name, "fsl-ls1028a-kontron-sl28"); >+ } >+} >+ >+int board_init(void) >+{ >+#ifdef CONFIG_ENV_IS_NOWHERE >+ gd->env_addr = (ulong)&default_environment[0]; #endif >+ >+#ifndef CONFIG_SYS_EARLY_PCI_INIT >+ pci_init(); >+#endif >+ >+ return 0; >+} >+ >+int board_eth_init(bd_t *bis) >+{ >+ return pci_eth_init(bis); >+} >+ >+void detail_board_ddr_info(void) >+{ >+ puts("\nDDR "); >+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); >+ print_ddr_info(0); >+} >+ >+#ifdef CONFIG_OF_BOARD_SETUP >+int ft_board_setup(void *blob, bd_t *bd) { >+ u64 base[CONFIG_NR_DRAM_BANKS]; >+ u64 size[CONFIG_NR_DRAM_BANKS]; >+ int nbanks = CONFIG_NR_DRAM_BANKS; >+ int i; >+ >+ ft_cpu_setup(blob, bd); >+ >+ /* fixup DT for the two GPP DDR banks */ >+ for (i = 0; i < nbanks; i++) { >+ base[i] = gd->bd->bi_dram[i].start; >+ size[i] = gd->bd->bi_dram[i].size; >+ } >+ >+ fdt_fixup_memory_banks(blob, base, size, nbanks); >+ >+ fdt_fixup_icid(blob); >+ >+ return 0; >+} >+#endif >diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c new file >mode 100644 index 0000000000..eb6d2dc909 >--- /dev/null >+++ b/board/kontron/sl28/spl.c >@@ -0,0 +1,9 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+ >+#include <common.h> >+#include <asm/spl.h> >+ >+void board_boot_order(u32 *spl_boot_list) { >+ spl_boot_list[0] = BOOT_DEVICE_SPI; >+} >diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig >new file mode 100644 index 0000000000..14bff90249 >--- /dev/null >+++ b/configs/kontron_sl28_defconfig >@@ -0,0 +1,102 @@ >+CONFIG_ARM=y >+CONFIG_TARGET_SL28=y >+CONFIG_SPL_LIBCOMMON_SUPPORT=y >+CONFIG_SPL_LIBGENERIC_SUPPORT=y >+CONFIG_SYS_MALLOC_F_LEN=0x4000 >+CONFIG_ENV_SIZE=0x2000 >+CONFIG_ENV_OFFSET=0x3e0000 >+CONFIG_ENV_SECT_SIZE=0x10000 >+CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 >+CONFIG_DM_GPIO=y >+CONFIG_SYS_FSL_SDHC_CLK_DIV=1 >+CONFIG_SPL_SERIAL_SUPPORT=y >+CONFIG_NR_DRAM_BANKS=2 >+CONFIG_SPL_SIZE_LIMIT=0x20000 >+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 >+CONFIG_SPL=y >+CONFIG_ENV_OFFSET_REDUND=0x3f0000 >+CONFIG_SPL_SPI_FLASH_SUPPORT=y >+CONFIG_SPL_SPI_SUPPORT=y >+# CONFIG_PSCI_RESET is not set >+CONFIG_SPL_TEXT_BASE=0x18010000 >+CONFIG_AHCI=y >+CONFIG_DISTRO_DEFAULTS=y >+CONFIG_FIT=y >+CONFIG_FIT_VERBOSE=y >+CONFIG_OF_BOARD_SETUP=y >+CONFIG_OF_STDOUT_VIA_ALIAS=y >+CONFIG_BOOTDELAY=10 >+CONFIG_USE_BOOTARGS=y >+CONFIG_BOARD_LATE_INIT=y >+CONFIG_SPL_BOARD_INIT=y >+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set >CONFIG_SPL_SEPARATE_BSS=y >+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y >+CONFIG_SPL_SPI_LOAD=y >+CONFIG_CMD_ASKENV=y >+CONFIG_CMD_GREPENV=y >+CONFIG_CMD_DM=y >+CONFIG_CMD_GPT=y >+CONFIG_CMD_I2C=y >+CONFIG_CMD_MMC=y >+CONFIG_CMD_PCI=y >+CONFIG_CMD_USB=y >+CONFIG_CMD_WDT=y >+CONFIG_CMD_CACHE=y >+CONFIG_MP=y >+CONFIG_OF_CONTROL=y >+CONFIG_SPL_OF_CONTROL=y >+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" >+CONFIG_OF_LIST="fsl-ls1028a-kontron-sl28 fsl-ls1028a-kontron-sl28-var3 fsl- >ls1028a-kontron-sl28-var4" >+CONFIG_MULTI_DTB_FIT=y >+CONFIG_ENV_IS_IN_SPI_FLASH=y >+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y >+CONFIG_NET_RANDOM_ETHADDR=y >+CONFIG_NETCONSOLE=y >+CONFIG_DM=y >+CONFIG_SPL_DM=y >+CONFIG_SPL_DM_SEQ_ALIAS=y >+CONFIG_SCSI_AHCI=y >+CONFIG_FSL_CAAM=y >+CONFIG_SYS_FSL_DDR3=y >+CONFIG_DM_I2C=y >+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y >+CONFIG_I2C_DEFAULT_BUS_NUMBER=0 >+CONFIG_I2C_MUX=y >+CONFIG_DM_MMC=y >+CONFIG_FSL_ESDHC=y >+CONFIG_DM_SPI_FLASH=y >+CONFIG_SPI_FLASH_WINBOND=y >+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y >+CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y >CONFIG_PHY_GIGE=y >+CONFIG_E1000=y CONFIG_FSL_ENETC=y CONFIG_NVME=y CONFIG_PCI=y >+CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y >CONFIG_PCIE_ECAM_GENERIC=y >+CONFIG_PCIE_LAYERSCAPE=y CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y >+CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y >+CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_NXP_FSPI=y CONFIG_USB=y >+CONFIG_DM_USB=y # CONFIG_SPL_DM_USB is not set >CONFIG_USB_XHCI_HCD=y >+CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SP805=y >+CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 >+CONFIG_OF_LIBFDT_OVERLAY=y >+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y >diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h >new file mode 100644 index 0000000000..3711f8b744 >--- /dev/null >+++ b/include/configs/kontron_sl28.h >@@ -0,0 +1,119 @@ >+/* SPDX-License-Identifier: GPL-2.0+ */ >+ >+#ifndef __SL28_H >+#define __SL28_H >+ >+#include <asm/arch/stream_id_lsch3.h> >+#include <asm/arch/config.h> >+#include <asm/arch/soc.h> >+ >+/* We don't use hwconfig but this has to be defined.. */ #define >+HWCONFIG_BUFFER_SIZE 256 >+ >+/* DDR */ >+#define CONFIG_DDR_ECC >+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER >+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef >+ >+#define CONFIG_VERY_BIG_RAM >+#define CONFIG_CHIP_SELECTS_PER_CTRL 4 >+#define CONFIG_DIMM_SLOTS_PER_CTLR 1 >+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL >+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 >+#define CONFIG_SYS_SDRAM_BASE > CONFIG_SYS_DDR_SDRAM_BASE >+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL >+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 >+ >+/* early stack pointer */ >+#define CONFIG_SYS_INIT_SP_ADDR > (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0) >+ >+/* memtest command */ >+#define CONFIG_SYS_MEMTEST_START 0x80000000 >+#define CONFIG_SYS_MEMTEST_END 0x9fffffff >+ >+/* SMP */ >+#define CPU_RELEASE_ADDR secondary_boot_func >+ >+/* generic timer */ >+#define COUNTER_FREQUENCY 25000000 >+ >+/* size of malloc() pool */ >+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * >1024) >+ >+/* early heap for SPL DM */ >+#define CONFIG_MALLOC_F_ADDR > CONFIG_SYS_FSL_OCRAM_BASE >+ >+/* serial port */ >+#define CONFIG_SYS_NS16550_SERIAL >+#define CONFIG_SYS_NS16550_REG_SIZE 1 >+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) >+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, >115200 } >+ >+#define CONFIG_SYS_CLK_FREQ 100000000 >+#define CONFIG_DDR_CLK_FREQ 100000000 >+#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) >+ >+/* MMC */ >+#ifdef CONFIG_MMC >+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 >+#endif >+ >+/* ethernet */ >+#define CONFIG_SYS_RX_ETH_BUFFER 8 >+ >+#ifdef CONFIG_SPL >+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" >+#define CONFIG_SPL_BSS_START_ADDR 0x80100000 >+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 >+#define CONFIG_SPL_MAX_SIZE 0x20000 >+#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + >0x9ff0) >+ >+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 >+#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 >+#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) >+#define CONFIG_SYS_SPI_U_BOOT_SIZE (0x100000 - >(CONFIG_SYS_SPI_U_BOOT_OFFS) >+#endif >+ >+#ifdef CONFIG_SPL_BUILD >+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE >+#else >+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE >+#endif >+ >+#define CONFIG_SYS_LOAD_ADDR > (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) >+ >+/* environment */ >+/* allow to overwrite serial and ethaddr */ #define >+CONFIG_ENV_OVERWRITE >+ >+#define CONFIG_LOADADDR 0x81000000 >+#define ENV_MEM_LAYOUT_SETTINGS \ >+ "scriptaddr=0x90000000\0" \ >+ "pxefile_addr_r=0x90100000\0" \ >+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ >+ "fdt_addr_r=0x83000000\0" \ >+ "ramdisk_addr_r=0x83100000\0" >+ >+#ifndef CONFIG_SPL_BUILD >+#define BOOT_TARGET_DEVICES(func) \ >+ func(MMC, mmc, 1) \ >+ func(MMC, mmc, 0) \ >+ func(NVME, nvme, 0) \ >+ func(USB, usb, 0) \ >+ func(DHCP, dhcp, 0) \ >+ func(PXE, pxe, 0) >+#include <config_distro_bootcmd.h> >+#else >+#define BOOTENV >+#endif >+ >+#define CONFIG_EXTRA_ENV_SETTINGS \ >+ "fdt_high=0xffffffffffffffff\0" \ >+ "initrd_high=0xffffffffffffffff\0" \ >+ "env_addr=0x203e0004\0" \ >+ "envload=env import -d -b ${env_addr}\0" \ >+ "install_rcw=source 20200000\0" \ >+ ENV_MEM_LAYOUT_SETTINGS \ >+ BOOTENV >+ >+#endif /* __SL28_H */ >-- >2.20.1
Kindly fix below build error: board/kontron/sl28/sl28.c: In function 'board_init': +board/kontron/sl28/sl28.c:52:2: error: implicit declaration of function 'pci_init'; did you mean 'phy_init'? [-Werror=implicit-function-declaration] + 52 | pci_init(); + | ^~~~~~~~ + | phy_init +board/kontron/sl28/sl28.c: At top level: +board/kontron/sl28/sl28.c:58:20: error: unknown type name 'bd_t'; did you mean 'gd_t'? + 58 | int board_eth_init(bd_t *bis) + | ^~~~ + | gd_t +board/kontron/sl28/sl28.c:71:32: error: unknown type name 'bd_t'; did you mean 'gd_t'? + 71 | int ft_board_setup(void *blob, bd_t *bd) + | ^~~~ + | gd_t +cc1: all warnings being treated as errors +make[2]: *** [board/kontron/sl28/sl28.o] Error 1 +make[1]: *** [board/kontron/sl28] Error 2 +make: *** [sub-make] Error 2 Regards Priyanka
