On Tue, Aug 04, 2020 at 09:53:04AM +0800, ub...@andestech.com wrote: > Hi Tom, > > Please pull some riscv updates: > > - add DM based reset driver for SiFive SoC's. > > Thanks > Rick > > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/714339244 > > The following changes since commit 68941e3b2c217907a49aa66af8bb65729b913397: > > Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2020-08-03 > 10:25:47 -0400) > > are available in the Git repository at: > > g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to ed50d3fae49b9dad58674b6609913beeac824e42: > > configs: reset: fu540: enable dm reset framework for SiFive (2020-08-04 > 09:19:41 +0800) >
Applied to u-boot/master, thanks! -- Tom
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