[PATCH] mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.

[haibo . chen]

From: Haibo Chen <haibo.c...@nxp.com>

Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.

Tested-by: Ji Luo <ji....@nxp.com>
Signed-off-by: Haibo Chen <haibo.c...@nxp.com>
---
 drivers/mmc/fsl_esdhc_imx.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 788677984b..b60623e0ce 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -631,6 +631,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct 
mmc *mmc, uint clock)
 {
        struct fsl_esdhc *regs = priv->esdhc_regs;
        int div = 1;
+       u32 time_out = 50;
 #ifdef ARCH_MXC
 #ifdef CONFIG_MX53
        /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
@@ -664,7 +665,14 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct 
mmc *mmc, uint clock)
 
        esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 
-       udelay(10000);
+       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_SDSTB)) {
+               if (time_out == 0) {
+                       printf("fsl_esdhc_imx: Internal clock never 
stabilised.\n");
+                       break;
+               }
+               time_out--;
+               udelay(2);
+       }
 
 #ifdef CONFIG_FSL_USDHC
        esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
-- 
2.17.1