On 9/18/20 4:26 PM, [email protected] wrote: >> This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration >> code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs >> have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. >> Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") >> Signed-off-by: Marek Vasut <[email protected]> >> Cc: Eric Nelson <[email protected]> >> Cc: Fabio Estevam <[email protected]> >> Cc: Stefano Babic <[email protected]> >> Reviewed-by: Fabio Estevam <[email protected]> > Applied to u-boot-imx, master, thanks !
I am tempted to say this should go into next, so it gets really really tested.
