>-----Original Message----- >From: U-Boot <[email protected]> On Behalf Of Wasim Khan >Sent: Tuesday, August 4, 2020 4:48 PM >To: Priyanka Jain <[email protected]>; Varun Sethi <[email protected]>; >Z.q. Hou <[email protected]> >Cc: [email protected]; Wasim Khan <[email protected]> >Subject: [PATCH v2 11/12] pci: layerscape: Add size check for config resource > >resource "config" is required to have minimum 8KB space as per hardware >documentation. > >Signed-off-by: Wasim Khan <[email protected]> >--- >Changes in V2: >- Updated commit description >- Fix CheckPatch issue > > drivers/pci/pcie_layerscape_rc.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > >diff --git a/drivers/pci/pcie_layerscape_rc.c >b/drivers/pci/pcie_layerscape_rc.c >index f9e3089..7e232be 100644 >--- a/drivers/pci/pcie_layerscape_rc.c >+++ b/drivers/pci/pcie_layerscape_rc.c >@@ -314,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev) > return ret; > } > >+ cfg_size = fdt_resource_size(&pcie_rc->cfg_res); >+ if (cfg_size < SZ_8K) { >+ printf("PCIe%d: %s Invalid size(0x%llx) for resource >\"config\",expected minimum 0x%x\n", >+ PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_8K); >+ return 0; >+ } >+ > /* > * Fix the pcie memory map address and PF control registers address > * for LS2088A series SoCs >@@ -323,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev) > if (svr == SVR_LS2088A || svr == SVR_LS2084A || > svr == SVR_LS2048A || svr == SVR_LS2044A || > svr == SVR_LS2081A || svr == SVR_LS2041A) { >- cfg_size = fdt_resource_size(&pcie_rc->cfg_res); > pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + > LS2088A_PCIE_PHYS_SIZE * pcie->idx; > pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size; >-- >2.7.4
Kindly fix build error on ls1021 platforms like ls1021aiot_qspi https://travis-ci.org/github/p-priyanka-jain/u-boot/jobs/729630555 Regards Priyanka
