Hi Marek On 1/7/21 7:16 PM, Marek Vasut wrote: > On 1/7/21 5:33 PM, Stephen Warren wrote: >> On 1/7/21 3:12 AM, Marek Vasut wrote: >>> The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words >>> after the descriptor. Use this to pad the descriptors to cacheline size and >>> remove the need for noncached memory altogether. Moreover, this lets Tegra >>> use the generic cache flush / invalidate operations. >> >> Tested-by: Stephen Warren <swar...@nvidia.com> >> Reviewed-by: Stephen Warren <swar...@nvidia.com> > > Thanks. > > This also really needs a TB/RB from ST before this is applied.
Tested-by: Patrice Chotard <patrice.chot...@foss.st.com> Tested on a stm32mp157c-ev1 board Thanks Patrice
