> -----Original Message-----
> From: Lim, Elly Siew Chin <[email protected]>
> Sent: Wednesday, February 24, 2021 9:54 AM
> To: [email protected]
> Cc: Marek Vasut <[email protected]>; Tan, Ley Foon
> <[email protected]>; See, Chin Liang <[email protected]>;
> Simon Goldschmidt <[email protected]>; Chee, Tien Fong
> <[email protected]>; Westergreen, Dalon
> <[email protected]>; Simon Glass <[email protected]>; Gan,
> Yau Wai <[email protected]>; Lim, Elly Siew Chin
> <[email protected]>
> Subject: [v2] Makefile: socfpga: Add target to generate hex output for
> combined spl and dtb
>
> From: Dalon Westergreen <[email protected]>
>
> Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel SOCFPGA
> SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex" is hex formatted
> spl with and offset of CONFIG_SPL_TEXT_BASE. It combines the spl image
> and dtb.
> "u-boot-spl-dtb.hex" is needed to generate the final configuration bitstream
> for Intel SOCFPGA SOC64 devices.
>
> Signed-off-by: Dalon Westergreen <[email protected]>
> Signed-off-by: Siew Chin Lim <[email protected]>
>
> ---
> v2: Update commit message
> ---
> ---
> Makefile | 11 ++++++-----
> include/configs/socfpga_soc64_common.h | 2 +-
> scripts/Makefile.spl | 8 ++++++++
> 3 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 4da46dea39..f1adc9aa23 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1263,11 +1263,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
> $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
> $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg
> -R .resetvec)
>
> -OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
> -
> -spl/u-boot-spl.hex: spl/u-boot-spl FORCE
> - $(call if_changed,objcopy)
> -
> binary_size_check: u-boot-nodtb.bin FORCE
> @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
> map_size=$(shell cat u-boot.map | \
> @@ -1935,6 +1930,12 @@ spl/u-boot-spl.bin: spl/u-boot-spl
> @:
> $(SPL_SIZE_CHECK)
>
> +spl/u-boot-spl-dtb.bin: spl/u-boot-spl
> + @:
> +
> +spl/u-boot-spl-dtb.hex: spl/u-boot-spl
> + @:
> +
> spl/u-boot-spl: tools prepare \
> $(if
> $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATD
> ATA),dts/dt.dtb) \
> $(if
> $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATD
> ATA),dts/dt.dtb)
> diff --git a/include/configs/socfpga_soc64_common.h
> b/include/configs/socfpga_soc64_common.h
> index fdcd7d3e9a..1af359466c 100644
> --- a/include/configs/socfpga_soc64_common.h
> +++ b/include/configs/socfpga_soc64_common.h
> @@ -200,7 +200,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
> * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
> *
> */
> -#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
> +#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex"
> #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
> #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
> diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index
> ea4e045769..625e06d0d9 100644
> --- a/scripts/Makefile.spl
> +++ b/scripts/Makefile.spl
> @@ -229,6 +229,9 @@ ifneq
> ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA
> 10),)
> INPUTS-y += $(obj)/$(SPL_BIN).sfp
> endif
>
> +INPUTS-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/u-boot-spl-
> dtb.hex
> +INPUTS-$(CONFIG_TARGET_SOCFPGA_AGILEX) += $(obj)/u-
> boot-spl-dtb.hex
Can use CONFIG_TARGET_SOCFPGA_SOC64.
Regards
Ley Foon
