On Fri, Feb 5, 2021 at 9:41 AM Sean Anderson <sean...@gmail.com> wrote:
>
> This series adds support for enhanced SPI modes. It was tested on a K210 (DWC
> SSI with QSPI flash).
>
> If anyone has a designware device with QSPI flash attached (especially a DW
> SSI
> APB device), I'd greatly appreciate them testing out this patch series.
>
> Many of the earlier patches in this series are general fixups and can be split
> off/merged separately if desired.
>
> Changes in v2:
> - Add more information to exec_op debug message
> - Actually mask interrupts
> - Merge CAP_{DUAL,QUAD,OCTAL} into CAP_ENHANCED
> - Fix some inconsistencies in register naming and usage
> - Moved some hunks between commits so things make more sense
>
> Sean Anderson (14):
> cmd: sf: Display errno on erase failure
> cmd: sf: Print error on test failure
> mtd: spi-nor-core: Fix typo in documentation
Applied to u-boot-spi/master
> mtd: spi-mem: Export spi_mem_default_supports_op
> spi: spi-mem: Add debug message for spi-mem ops
Commented.
> spi: dw: Log status register on timeout
> spi: dw: Actually mask interrupts
> spi: dw: Switch to capabilities
> spi: dw: Rewrite poll_transfer logic
> spi: dw: Add ENHANCED cap
> spi: dw: Define registers for enhanced mode
> spi: dw: Support enhanced SPI
> spi: dw: Support clock stretching
Any testing on these? it's better to have an Ack from respective
driver authors or users. Once done, please send a series for dw-spi
patches.
> riscv: k210: Enable QSPI for spi3
I think Rick can pick this via risc-v tree.
Jagan.
