On Fri, Feb 26, 2021 at 09:53:24AM +0800, Leo Liang wrote: > Hi Tom, > > Please pull some RISC-V updates. > CI result: > https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/6505 > > The following changes since commit cbe607b920bc0827d8fe379ed4f5ae4e2058513e: > > Merge tag 'xilinx-for-v2021.04-rc3' of > https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze (2021-02-23 > 10:45:55 -0500) > > are available in the Git repository at: > > g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 5540294fa48598bf1aa8aa4d9084506a19bbd64c: > > riscv: k210: Enable QSPI for spi3 (2021-02-25 18:06:08 +0800) >
Applied to u-boot/master, thanks! -- Tom
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