> -----Original Message-----
> From: Lim, Elly Siew Chin <[email protected]>
> Sent: Saturday, February 27, 2021 12:58 AM
> To: [email protected]
> Cc: Marek Vasut <[email protected]>; Tan, Ley Foon
> <[email protected]>; See, Chin Liang <[email protected]>;
> Simon Goldschmidt <[email protected]>; Chee, Tien Fong
> <[email protected]>; Westergreen, Dalon
> <[email protected]>; Simon Glass <[email protected]>; Gan,
> Yau Wai <[email protected]>; Lim, Elly Siew Chin
> <[email protected]>
> Subject: [RESEND v4 7/7] Makefile: socfpga: Add target to generate hex
> output for combined spl and dtb
>
> From: Dalon Westergreen <[email protected]>
>
> Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel SOCFPGA
> SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex"
> is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It combines
> the spl image and dtb. "u-boot-spl-dtb.hex" is needed to generate the final
> configuration bitstream for Intel SOCFPGA SOC64 devices.
>
> Signed-off-by: Dalon Westergreen <[email protected]>
> Signed-off-by: Siew Chin Lim <[email protected]>
>
> ---
> v4:
> - Replace CONFIG_TARGET_SOCFPGA_STRATIX10/AGILEX with
> CONFIG_TARGET_SOCFPGA_SOC64.
> - Add this patch into 'VAB' series because it is depending on
> CONFIG_TARGET_SOCFPGA_SOC64 patch.
> ---
> Makefile | 11 ++++++-----
> include/configs/socfpga_soc64_common.h | 2 +-
> scripts/Makefile.spl | 7 +++++++
> 3 files changed, 14 insertions(+), 6 deletions(-)
Reviewed-by: Ley Foon Tan <[email protected]>
Regards
Ley Foon
