> -----Original Message-----
> From: Lim, Elly Siew Chin <[email protected]>
> Sent: Wednesday, March 24, 2021 2:20 PM
> To: [email protected]
> Cc: Marek Vasut <[email protected]>; Tan, Ley Foon
> <[email protected]>; See, Chin Liang <[email protected]>;
> Simon Goldschmidt <[email protected]>; Chee, Tien Fong
> <[email protected]>; Westergreen, Dalon
> <[email protected]>; Simon Glass <[email protected]>; Gan,
> Yau Wai <[email protected]>; Lim, Elly Siew Chin
> <[email protected]>
> Subject: [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
>
> Changed to store QSPI reference clock in kHz instead of Hz in boot scratch
> cold0 register for Stratix10 and Agilex.
>
> This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4
> bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI
> reference clock.
> Due to limited bits, QSPI reference clock frequency is converted to kHz from
> Hz.
>
> Signed-off-by: Siew Chin Lim <[email protected]>
> Signed-off-by: Tien Fong Chee <[email protected]>
>
> ---
> v2:
> - Rename mbox_qspi_set_controller_clk_hz function to
> cm_set_qspi_controller_clk_hz function and move to clock_manager.c.
> - Remove CLOCK_1K macro from socfpga_soc64_common.h
> - Sort include file list by alphabetical order in mailbox_s10.c
> ---
>
Reviewed-by: Ley Foon Tan <[email protected]>
