On Sat, May 1, 2021 at 5:13 PM Andrey Zhizhikin <[email protected]> wrote: > > Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ() > macro, which expands the value provided to the Hz range without taking into > account the precise Hz setting. This causes the frequency of 266 MHz not ot > be found in the imx8mm_fracpll_tbl, since it is entered there with a > precise Hz value. This in turn causes the boot hang in SPL, as proper DDR > fracpll frequency cannot be determined. > > Correct the value in imx8mm_fracpll_tbl to match the one expanded by > MHZ(266) macro, rounding it down to MHz range only. > > Signed-off-by: Andrey Zhizhikin <[email protected]> > Cc: Stefano Babic <[email protected]> > Cc: Fabio Estevam <[email protected]> > Cc: "NXP i.MX U-Boot Team" <[email protected]> > Cc: Peng Fan <[email protected]> > Cc: Simon Glass <[email protected]> > Cc: Ye Li <[email protected]> > Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")
Reviewed-by: Fabio Estevam <[email protected]>
