Hi,
snip.
>>> +
>>> + priv->base = (void __iomem *)addr;
>>
>> But this assignment should be done in probe where you copy data from
>> plat structures to priv structures.
>
> Do you mean priv->base = (void __iomem *)plat->addr?
yes.
>>> +
>>> + clk_in1 = dev_read_u32_default(dev, "clock-frequency", 0);
>>
>> This is not the part of DT binding. You should be able to get that
>> frequencies via clock framework.
>
> Can you provide some hints about this? I am new to clock driver.
You should look at drivers/serial/serial_zynq.c where you can find out
clk_get_by_index(), clk_get_rate(), clk_enable()
That clk_get_rate() is the function you should use to get that frequency.
snip.
>
>>> + { /* sentinel */ }
>>> +};
>>> +
>>> +U_BOOT_DRIVER(clk_wzrd) = {
>>> + .name = "zynq-clk-wizard",
>>> + .id = UCLASS_CLK,
>>> + .of_match = clk_wzrd_ids,
>>> + .ops = &clk_wzrd_ops,
>>> + .probe = clk_wzrd_probe,
>>> + .of_to_plat = clk_wzrd_of_to_plat,
>>> + .priv_auto = sizeof(struct clkwzd),
>>
>> you need to get memory for .plat_auto here.
>
> Okay.
>
> On the other hand, if we want to add set_phase feature to clock wizard,
> can you make some suggestions? I checked the clk-uclass and it does not
> seem to be supported.
Then you have to add it to uclass first but don't know content here.
>
> Thanks,
> Zhengxun
>
>
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And get rid of these. Next time I won't reply to this email. Sorry.
Thanks,
Michal
