There is a QSPI NOR flash part on the board. Because this chip isn't
yet supported in Linux, but it is supported in U-Boot, and the
face that the RPC_SPI compatible names are different in U-Boot and
Linux, the device tree updates are confined to -u-boot.dtsi files.
Signed-off-by: Adam Ford <aford...@gmail.com>
diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
index a0c0a7f35c..06271537b7 100644
--- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
+++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
@@ -4,11 +4,19 @@
*/
/ {
+ aliases {
+ spi0 = &rpc;
+ };
+
soc {
u-boot,dm-pre-reloc;
};
};
+&avb {
+ phy-mode = "rgmii-txid";
+};
+
&cpg {
u-boot,dm-pre-reloc;
};
@@ -25,6 +33,25 @@
u-boot,dm-pre-reloc;
};
+&rpc {
+ compatible = "renesas,rcar-gen3-rpc";
+ num-cs = <1>;
+ spi-max-frequency = <40000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&sdhi0 {
/delete-property/ cd-gpios;
};
diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
index a0c0a7f35c..be0ce54e55 100644
--- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
+++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
@@ -4,6 +4,10 @@
*/
/ {
+ aliases {
+ spi0 = &rpc;
+ };
+
soc {
u-boot,dm-pre-reloc;
};
@@ -25,6 +29,25 @@
u-boot,dm-pre-reloc;
};
+&rpc {
+ compatible = "renesas,rcar-gen3-rpc";
+ num-cs = <1>;
+ spi-max-frequency = <40000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&sdhi0 {
/delete-property/ cd-gpios;
};
diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
index eef200af2d..228391e0df 100644
--- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
+++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
@@ -4,6 +4,10 @@
*/
/ {
+ aliases {
+ spi0 = &rpc;
+ };
+
soc {
u-boot,dm-pre-reloc;
};
@@ -25,6 +29,25 @@
u-boot,dm-pre-reloc;
};
+&rpc {
+ compatible = "renesas,rcar-gen3-rpc";
+ num-cs = <1>;
+ spi-max-frequency = <40000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&sdhi0 {
/delete-property/ cd-gpios;
sd-uhs-sdr12;
diff --git a/configs/r8a774a1_beacon_defconfig
b/configs/r8a774a1_beacon_defconfig
index 58d3f9f019..ff29a40d15 100644
--- a/configs/r8a774a1_beacon_defconfig
+++ b/configs/r8a774a1_beacon_defconfig
@@ -17,7 +17,9 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@@ -46,6 +48,10 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
@@ -55,6 +61,9 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/r8a774b1_beacon_defconfig
b/configs/r8a774b1_beacon_defconfig
index c0d2d1bf53..537343eea0 100644
--- a/configs/r8a774b1_beacon_defconfig
+++ b/configs/r8a774b1_beacon_defconfig
@@ -17,7 +17,9 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@@ -47,6 +49,10 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_BITBANGMII=y
CONFIG_PHY_REALTEK=y
@@ -60,6 +66,9 @@ CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/r8a774e1_beacon_defconfig
b/configs/r8a774e1_beacon_defconfig
index 800c7b8c79..8b3b86007f 100644
--- a/configs/r8a774e1_beacon_defconfig
+++ b/configs/r8a774e1_beacon_defconfig
@@ -17,7 +17,9 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@@ -46,6 +48,10 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
@@ -55,6 +61,9 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
--
2.25.1
