Hi Michal, El mar, 22 jun 2021 a las 13:16, Michal Simek (<mon...@monstr.eu>) escribió: > > > > On 6/22/21 12:42 PM, Alvaro Gamez wrote: > > Hi again > > > > El jue, 17 jun 2021 a las 15:07, Alvaro Gamez > > (<alvaro.ga...@hazent.com>) escribió: > >> > >> Hi! > >> > >> I'm trying to use buildroot to generate a system for the Digilent > >> Genesys ZU board, which is based on the zynqmp SOC. > >> I'm having trouble getting it to boot, and I was hoping I could get > >> some guidance on what to do next. My issue is basically that > >> nothing seems to work, since I don't have an output at all on the > >> serial console. > >> > >> I'm using u-boot version 2021.04, which has the latest patches from > >> Luca Ceresoli that should allow booting completely via u-boot and > >> u-boot SPL, without using Xilinx' FSBL. My method of cross compiling > >> is via buildroot version 2021.05, which eases the process of gathering > >> also Arm Trusted Firmware, building the linux kernel and filesystem, etc. > >> > >> Out of Digilent's reference design, Vivado/Vitis generates for me > >> configuration object pm_cfg_obj.c and PSU init file psu_init_gpl.c, > >> which shall be fed to u-boot. Alongside these files, I use PMU firmware > >> built by Luca at > >> https://github.com/lucaceresoli/zynqmp-pmufw-binaries/raw/master/bin/pmufw-v2018.3.bin > >> > >> To provide Arm Trusted Firmware, I'm passing buildroot the same > >> configuration as already exists on configs/zynqmp_zcu106_defconfig > >> which is version 1.5 of : > >> https://github.com/ARM-software/arm-trusted-firmware.git > >> but I don't think my board has reached the state of needing this firmware > >> yet, > >> since I don't get any SPL serial console output. > >> > >> The device tree I'm using is extracted from Digilent's kernel image, > >> and matches perfectly with the one generated by petalinux for this > >> Digilent's Vivado design, so it should be correct > >> > >> Provided image by Digilent follows the Xilinx' booting workflow, so > >> only a BOOT.BIN file is on the sdcard which includes xilinx' FSBL, PMU > >> firmware with configuration object, u-boot, kernel, device tree, etc, > >> so at least I know that the board is fine as this firmware works > >> flawlessly. I also was able to load the kernel and device tree as > >> built by buildroot over this instance of u-boot, so at least I can > >> load my own kernel, but I can't progress deeper than that. > > > > I've been able to load u-boot proper via Xilinx FSBL, so it seems that my > > u-boot > > configuration is not very far from what should be, but I'm still > > unable to see any > > reaction when trying to load SPL. I'm attaching my u-boot configuration, > > just > > in case any of you can provide any guidance on this. > > > > CONFIG_ARM=y > > CONFIG_ARCH_ZYNQMP=y > > CONFIG_SYS_TEXT_BASE=0x8000000 > > CONFIG_SYS_MALLOC_F_LEN=0x8000 > > CONFIG_ENV_OFFSET=0x100000 > > CONFIG_ENV_SECT_SIZE=0x20000 > > CONFIG_DM_GPIO=y > > CONFIG_SPL=y > > CONFIG_DEBUG_UART_BASE=0xFF000000 > > CONFIG_DEBUG_UART_CLOCK=100000000 > > CONFIG_XILINX_PS_INIT_FILE="/tmp/psu_init_gpl.c" > > CONFIG_PMUFW_INIT_FILE="/tmp/pmufw-v2018.3.bin" > > CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE="/tmp/pm_cfg_obj.bin" > > CONFIG_ZYNQMP_USB=y > > CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0" > > please make sure that default DT points to DT file for your board.
I am using my own DT file, orig.dts, which is copied to arch/arm/dts and its Makefile modified to include it as a target of ZYNQMP. Does it matter what's here in that case? In any case, I've just changed it to my DT, but nothing different happens. > > > > CONFIG_DEBUG_UART=y > > CONFIG_DISTRO_DEFAULTS=y > > CONFIG_FIT=y > > CONFIG_FIT_VERBOSE=y > > CONFIG_LOG=y > > # CONFIG_DISPLAY_CPUINFO is not set > > CONFIG_BOARD_EARLY_INIT_R=y > > CONFIG_CMD_BOOTMENU=y > > CONFIG_CMD_THOR_DOWNLOAD=y > > CONFIG_CMD_MEMTEST=y > > CONFIG_SYS_ALT_MEMTEST=y > > CONFIG_CMD_CLK=y > > CONFIG_CMD_DFU=y > > CONFIG_CMD_FPGA_LOADBP=y > > CONFIG_CMD_FPGA_LOADP=y > > CONFIG_CMD_FPGA_LOAD_SECURE=y > > CONFIG_CMD_GPIO=y > > CONFIG_CMD_GPT=y > > CONFIG_CMD_I2C=y > > CONFIG_CMD_MMC=y > > CONFIG_CMD_SDRAM=y > > CONFIG_CMD_SPI=y > > CONFIG_CMD_USB=y > > CONFIG_CMD_TFTPPUT=y > > CONFIG_CMD_TIME=y > > CONFIG_CMD_TIMER=y > > CONFIG_CMD_EXT4_WRITE=y > > CONFIG_CMD_UBI=y > > CONFIG_SPL_OF_CONTROL=y > > CONFIG_OF_EMBED=y > > CONFIG_ENV_IS_NOWHERE=y > > CONFIG_ENV_IS_IN_FAT=y > > CONFIG_ENV_IS_IN_SPI_FLASH=y > > CONFIG_NET_RANDOM_ETHADDR=y > > CONFIG_CLK_ZYNQMP=y > > CONFIG_DFU_MMC=y > > CONFIG_DFU_RAM=y > > CONFIG_USB_FUNCTION_FASTBOOT=y > > CONFIG_FASTBOOT_FLASH=y > > CONFIG_FASTBOOT_FLASH_MMC_DEV=0 > > CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > > CONFIG_FPGA_XILINX=y > > CONFIG_FPGA_ZYNQMPPL=y > > CONFIG_XILINX_GPIO=y > > CONFIG_DM_I2C=y > > CONFIG_SYS_I2C_CADENCE=y > > CONFIG_I2C_MUX=y > > CONFIG_I2C_MUX_PCA954x=y > > CONFIG_LED=y > > CONFIG_LED_GPIO=y > > CONFIG_MISC=y > > CONFIG_MMC_IO_VOLTAGE=y > > CONFIG_MMC_UHS_SUPPORT=y > > CONFIG_MMC_SDHCI=y > > CONFIG_MMC_SDHCI_ZYNQ=y > > CONFIG_MTD=y > > CONFIG_SPI_FLASH_BAR=y > > CONFIG_SPI_FLASH_ISSI=y > > CONFIG_SPI_FLASH_MACRONIX=y > > CONFIG_SPI_FLASH_SPANSION=y > > CONFIG_SPI_FLASH_STMICRO=y > > CONFIG_SPI_FLASH_WINBOND=y > > # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > > CONFIG_MTD_UBI_BEB_LIMIT=0 > > CONFIG_PHY_MARVELL=y > > CONFIG_PHY_REALTEK=y > > CONFIG_PHY_TI=y > > CONFIG_PHY_VITESSE=y > > CONFIG_PHY_FIXED=y > > CONFIG_PHY_GIGE=y > > CONFIG_MII=y > > CONFIG_ZYNQ_GEM=y > > CONFIG_DEBUG_UART_ANNOUNCE=y > > CONFIG_ZYNQ_SERIAL=y > > CONFIG_SPI=y > > CONFIG_ZYNQMP_GQSPI=y > > CONFIG_USB=y > > CONFIG_USB_XHCI_HCD=y > > CONFIG_USB_XHCI_DWC3=y > > CONFIG_USB_DWC3=y > > CONFIG_USB_DWC3_GENERIC=y > > CONFIG_USB_ULPI_VIEWPORT=y > > CONFIG_USB_ULPI=y > > CONFIG_USB_GADGET=y > > CONFIG_USB_GADGET_MANUFACTURER="Xilinx" > > CONFIG_USB_GADGET_VENDOR_NUM=0x03FD > > CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 > > CONFIG_USB_FUNCTION_THOR=y > > CONFIG_PANIC_HANG=y > > # CONFIG_EFI_LOADER is not set > > And you should normally just add psu_init_gpl.c/h to > board/xilinx/zynqmp/<dt_name>/* and run export DEVICE_TREE=<dt_name> and > add dt file to arch/arm/dts + wiring in Makefile. I should have mentioned that I am building uboot via Buildroot, so buildroot is taking care of this, by compiling my own dts, which I did in fact had to manually add under dtb-$(CONFIG_ARCH_ZYNQMP) += \ (as explained above too). The same happens with psu_init_gpl.* files, which are managed by Buildroot too, so I can be relatively sure that these steps are correct. The fact that uboot proper boots also seems to confirm this. > The rest should be done automatically. > If you export link to BL31 (atf) > export BL31=/tmp/bl31.bin Buildroot already manages that for me too, thankfully > after make you will get spl/boot.bin and u-boot.itb. And just copy them > to SD card and boot from it. If you use different boot medium just check > that addresses which u-boot SPL is looking for. Ah, things are different here. I am using u-boot.elf file. Trying to compile itb results in the following error: HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o HOSTCC scripts/kconfig/zconf.tab.o HOSTLD scripts/kconfig/conf scripts/kconfig/conf --syncconfig Kconfig GEN include/autoconf.mk.dep CFG u-boot.cfg CFG spl/u-boot.cfg GEN include/autoconf.mk GEN spl/include/autoconf.mk ===================== WARNING ====================== CONFIG_OF_EMBED is enabled. This option should only be used for debugging purposes. Please use CONFIG_OF_SEPARATE for boards in mainline. UPD include/generated/timestamp_autogenerated.h See doc/README.fdt-control for more info. ==================================================== COPY u-boot.its cp: missing destination file operand after 'u-boot.its' Try 'cp --help' for more information. make[2]: *** [Makefile:1303: u-boot.its] Error 1 make[2]: *** Waiting for unfinished jobs.... CFGCHK u-boot.cfg However, regardless of what target file I am using for uboot proper, shouldn't I see some output from SPL? > Enabling Debug uart makes also sense. Yeah, it's enabled by default. I only sent the subset of configuration that differs from the default. Here is the whole .config file stripped of comments blank lines, to make it more manageable. CONFIG_CREATE_ARCH_SYMLINK=y CONFIG_LINKER_LIST_ALIGN=8 CONFIG_ARM=y CONFIG_SYS_ARCH="arm" CONFIG_SYS_CPU="armv8" CONFIG_SYS_SOC="zynqmp" CONFIG_SYS_VENDOR="xilinx" CONFIG_SYS_BOARD="zynqmp" CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp" CONFIG_ARM64=y CONFIG_STATIC_RELA=y CONFIG_DMA_ADDR_T_64BIT=y CONFIG_ARM_ASM_UNIFIED=y CONFIG_SYS_ARM_ARCH=8 CONFIG_SYS_CACHE_SHIFT_6=y CONFIG_SYS_CACHELINE_SIZE=64 CONFIG_SYS_ARM_CACHE_WRITEBACK=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARM_SMCCC=y CONFIG_ARM64_SUPPORT_AARCH32=y CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=4 CONFIG_SYS_MEMTEST_START=0 CONFIG_SYS_MEMTEST_END=0x1000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 CONFIG_ERR_PTR_OFFSET=0x0 CONFIG_SPL_SIZE_LIMIT=0x0 CONFIG_SPL=y CONFIG_BOOTSTAGE_STASH_ADDR=0 CONFIG_DEBUG_UART_BASE=0xFF000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_IDENT_STRING="" CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_BOOT_INIT_FILE="" CONFIG_ZYNQ_SDHCI_MAX_FREQ=200000000 CONFIG_XILINX_PS_INIT_FILE="/tmp/psu_init_gpl.c" CONFIG_BOOT_SCRIPT_OFFSET=0x3E80000 CONFIG_PMUFW_INIT_FILE="/home/sslayer/.buildroot-dl/uboot/pmufw-v2018.3.bin" CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE="/home/sslayer/Proyectos/ART/SAR/SAR.git/Genesys/output/build/uboot-2021.04/pm_cfg_obj.bin" CONFIG_ZYNQMP_USB=y CONFIG_DEFINE_TCM_OCM_MMAP=y CONFIG_CMD_ZYNQMP=y CONFIG_PSCI_RESET=y CONFIG_IMX_DCD_ADDR=0x00910000 CONFIG_SPL_PAYLOAD="u-boot.bin" CONFIG_BUILD_TARGET="" CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0" CONFIG_DEBUG_UART=y CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_SYS_MALLOC_F=y CONFIG_EXPERT=y CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y CONFIG_PHYS_64BIT=y CONFIG_SPL_IMAGE="spl/u-boot-spl.bin" CONFIG_PLATFORM_ELFENTRY="_start" CONFIG_STACK_SIZE=0x4000000 CONFIG_SYS_SRAM_BASE=0x0 CONFIG_SYS_SRAM_SIZE=0x0 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x0 CONFIG_FIT_ENABLE_SHA256_SUPPORT=y CONFIG_FIT_FULL_CHECK=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_PRINT=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="" CONFIG_HAVE_SYS_TEXT_BASE=y CONFIG_ARCH_FIXUP_FDT_MEMORY=y CONFIG_BOOTSTAGE_STASH_SIZE=0x1000 CONFIG_AUTOBOOT=y CONFIG_BOOTDELAY=2 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="" CONFIG_MENU=y CONFIG_LOGLEVEL=4 CONFIG_SPL_LOGLEVEL=4 CONFIG_TPL_LOGLEVEL=4 CONFIG_LOG=y CONFIG_LOG_MAX_LEVEL=6 CONFIG_LOG_DEFAULT_LEVEL=6 CONFIG_LOG_CONSOLE=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BOARD_LATE_INIT=y CONFIG_HASH=y CONFIG_SUPPORT_SPL=y CONFIG_SPL_FRAMEWORK=y CONFIG_SPL_SYS_STACK_F_CHECK_BYTE=0xaa CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_RAW_IMAGE_SUPPORT=y CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_BANNER_PRINT=y CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=1 CONFIG_SPL_DM_SPI_FLASH=y CONFIG_CMDLINE=y CONFIG_HUSH_PARSER=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_SYS_LONGHELP=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_SYS_PROMPT_HUSH_PS2="> " CONFIG_SYS_XTRACE="y" CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y CONFIG_CMD_BOOTD=y CONFIG_CMD_BOOTM=y CONFIG_CMD_BOOTI=y CONFIG_BOOTM_LINUX=y CONFIG_BOOTM_NETBSD=y CONFIG_BOOTM_PLAN9=y CONFIG_BOOTM_RTEMS=y CONFIG_BOOTM_VXWORKS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_ELF=y CONFIG_CMD_FDT=y CONFIG_CMD_GO=y CONFIG_CMD_RUN=y CONFIG_CMD_IMI=y CONFIG_CMD_XIMG=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_EXPORTENV=y CONFIG_CMD_IMPORTENV=y CONFIG_CMD_EDITENV=y CONFIG_CMD_SAVEENV=y CONFIG_CMD_ENV_EXISTS=y CONFIG_CMD_CRC32=y CONFIG_CMD_MEMORY=y CONFIG_CMD_RANDOM=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_SYS_ALT_MEMTEST_BITFLIP=y CONFIG_CMD_LZMADEC=y CONFIG_CMD_UNLZ4=y CONFIG_CMD_UNZIP=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y CONFIG_CMD_FASTBOOT=y CONFIG_CMD_FLASH=y CONFIG_CMD_FPGA=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_RANDOM_UUID=y CONFIG_CMD_I2C=y CONFIG_CMD_LOADB=y CONFIG_CMD_LOADS=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_SDRAM=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_DEFAULT_SPI_BUS=0 CONFIG_DEFAULT_SPI_MODE=0 CONFIG_CMD_USB=y CONFIG_CMD_ECHO=y CONFIG_CMD_ITEST=y CONFIG_CMD_SOURCE=y CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y CONFIG_CMD_BOOTP=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTPATH=y CONFIG_BOOTP_DNS=y CONFIG_BOOTP_GATEWAY=y CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTP_PXE=y CONFIG_BOOTP_PXE_CLIENTARCH=0x16 CONFIG_BOOTP_VCI_STRING="U-Boot.armv8" CONFIG_CMD_TFTPBOOT=y CONFIG_CMD_TFTPPUT=y CONFIG_NET_TFTP_VARS=y CONFIG_CMD_NFS=y CONFIG_CMD_MII=y CONFIG_CMD_MDIO=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y CONFIG_CMD_BLOCK_CACHE=y CONFIG_CMD_LED=y CONFIG_CMD_TIME=y CONFIG_CMD_SLEEP=y CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_SYSBOOT=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="" CONFIG_MTDPARTS_DEFAULT="" CONFIG_CMD_UBI=y CONFIG_CMD_UBIFS=y CONFIG_PARTITIONS=y CONFIG_DOS_PARTITION=y CONFIG_SPL_DOS_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=128 CONFIG_EFI_PARTITION_ENTRIES_OFF=0 CONFIG_SPL_EFI_PARTITION=y CONFIG_PARTITION_UUIDS=y CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SUPPORT_OF_CONTROL=y CONFIG_DTC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts" CONFIG_ENV_SUPPORT=y CONFIG_SAVEENV=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:auto" CONFIG_ENV_FAT_FILE="uboot.env" CONFIG_ENV_ADDR=0x0 CONFIG_SYS_MMC_ENV_DEV=0 CONFIG_SYS_MMC_ENV_PART=0 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_BLOCKSIZE=1468 CONFIG_TFTP_WINDOWSIZE=1 CONFIG_SERVERIP_FROM_PROXYDHCP_DELAY_MS=100 CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_DM_WARN=y CONFIG_DM_DEVICE_REMOVE=y CONFIG_DM_STDIO=y CONFIG_DM_SEQ_ALIAS=y CONFIG_SPL_DM_INLINE_OFNODE=y CONFIG_SIMPLE_BUS=y CONFIG_SPL_SIMPLE_BUS=y CONFIG_OF_TRANSLATE=y CONFIG_DM_DEV_READ_INLINE=y CONFIG_BLK=y CONFIG_HAVE_BLOCK_DEVICE=y CONFIG_SPL_BLK=y CONFIG_BLOCK_CACHE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_ZYNQMP=y CONFIG_DFU=y CONFIG_DFU_OVER_USB=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x100000 CONFIG_FASTBOOT_BUF_SIZE=0x6000000 CONFIG_FASTBOOT_USB_DEV=0 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_GPT_NAME="gpt" CONFIG_FASTBOOT_MBR_NAME="mbr" CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FIRMWARE=y CONFIG_SPL_FIRMWARE=y CONFIG_ARM_PSCI_FW=y CONFIG_ZYNQMP_FIRMWARE=y CONFIG_FPGA=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_XILINX_GPIO=y CONFIG_ZYNQ_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_INPUT=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MAILBOX=y CONFIG_ZYNQMP_IPI=y CONFIG_MISC=y CONFIG_MMC=y CONFIG_MMC_WRITE=y CONFIG_DM_MMC=y CONFIG_SPL_DM_MMC=y CONFIG_MMC_QUIRKS=y CONFIG_MMC_HW_PARTITIONING=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_VERBOSE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ZYNQ_SDHCI_MIN_FREQ=0 CONFIG_MTD_PARTITIONS=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=0 CONFIG_SF_DEFAULT_CS=0 CONFIG_SF_DEFAULT_MODE=3 CONFIG_SF_DEFAULT_SPEED=1000000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_UNLOCK_ALL=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=0 CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_NETDEVICES=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_BAUDRATE=115200 CONFIG_REQUIRE_SERIAL_CONSOLE=y CONFIG_SERIAL_PRESENT=y CONFIG_SPL_SERIAL_PRESENT=y CONFIG_DM_SERIAL=y CONFIG_SPL_DM_SERIAL=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_SHIFT=0 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SPI_MEM=y CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_SPL_DM_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_SDP_LOADADDR=0 CONFIG_USB_GADGET_DUALSPEED=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_FS_EXT4=y CONFIG_EXT4_WRITE=y CONFIG_FS_FAT=y CONFIG_FAT_WRITE=y CONFIG_FS_FAT_MAX_CLUSTSIZE=65536 CONFIG_LIB_UUID=y CONFIG_PRINTF=y CONFIG_SPL_PRINTF=y CONFIG_SPRINTF=y CONFIG_SPL_SPRINTF=y CONFIG_STRTO=y CONFIG_SPL_STRTO=y CONFIG_IMAGE_SPARSE=y CONFIG_IMAGE_SPARSE_FILLBUF_SIZE=0x80000 CONFIG_SYS_HZ=1000 CONFIG_SPL_USE_TINY_PRINTF=y CONFIG_PANIC_HANG=y CONFIG_REGEX=y CONFIG_LIB_RAND=y CONFIG_RBTREE=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_MD5=y CONFIG_LZ4=y CONFIG_LZMA=y CONFIG_LZO=y CONFIG_GZIP=y CONFIG_ZLIB=y CONFIG_OF_LIBFDT=y CONFIG_OF_LIBFDT_ASSUME_MASK=0 CONFIG_SPL_OF_LIBFDT=y CONFIG_SPL_OF_LIBFDT_ASSUME_MASK=0xff CONFIG_TPL_OF_LIBFDT_ASSUME_MASK=0xff CONFIG_LIB_ELF=y CONFIG_MKIMAGE_DTC_PATH="dtc" > Thanks, > Michal > > > -- > Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 > w: www.monstr.eu p: +42-0-721842854 > Maintainer of Linux kernel - Xilinx Microblaze > Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs > U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs > Thanks! Best regards -- Álvaro Gámez Machado
