Hi Tim, (please try to quote correctly upon replying, your answers are hard to read)
On Tuesday 26 October 2010 09:21:50 Tim Rachman wrote: > > According to your useful guides in our previous Emails, I examined again > > my ddr sdram parameters that i had set in u-boot. I'm interfacing > > HYB25D512160AT–7 to PPC440EP, with 133MHz plb frequency. > > What SDRAM/DDR init code are you using? Is it > arch/powerpc/cpu/ppc4xx/sdram.c? > > > Yes, I am. But I changed some parameters according to HYB25D512160AT–7 > datasheet. Which changes did you make exactly? Are you using the sdram_tr1_set() function to "fine-tune" the controller settings? <snip> > A point: Our custom board doesn't have PCI , Is it possible that some > setting in PCI routins of yosemite BSP has effect on their shared PLB BUS? No, I don't think so. But you should create a "real" board port for your custom board and remove such unused features as PCI in this process. > BTW, I focus on SDRAM configuration more, Hopefully problem will be solved. Good luck. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: [email protected] _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
