On Sun, Jun 13, 2021 at 4:49 PM Siew Chin Lim <[email protected]> wrote: > > From: Tien Fong Chee <[email protected]> > > The DDR subsystem in Diamond Mesa is consisted of controller, PHY, > memory reset manager and memory clock manager. > > Configuration settings of controller, PHY and memory reset manager > is come from DDR handoff data in bitstream, which contain the register > base addresses and user settings from tool. > > Configuration settings of memory clock manager is come from the HPS > handoff data in bitstream, however the register base address is defined > in device tree. > > The calibration is fully done in HPS, which requires IMEM and DMEM > binaries loading to PHY SRAM for running this calibration, both > IMEM and DMEM binaries are also part of bitstream, this bitstream > would be loaded to OCRAM by SDM, and configured by DDR driver. > > Signed-off-by: Siew Chin Lim <[email protected]> > Signed-off-by: Tien Fong Chee <[email protected]> > > --- > v3: > - Sorting header > - Used prefix OPM_xxx > - Simplify the code with do...while loop. > - Created common function for processing handoff > - Adding function of calibration data feedback to LPDDR4 controllers > > v2: > - Move is_ddr_init_skipped and its helper functions to DDR driver and > converted function to positive checking > - Using GENMASK() macro > - Fixed typo > - Return status of subfunction > - Changed dm to n5x > --- > arch/arm/mach-socfpga/include/mach/firewall.h | 6 + > .../include/mach/system_manager_soc64.h | 10 +- > drivers/ddr/altera/Makefile | 3 +- > drivers/ddr/altera/sdram_n5x.c | 2298 +++++++++++++++++ > drivers/ddr/altera/sdram_soc64.c | 70 + > drivers/ddr/altera/sdram_soc64.h | 1 + > 6 files changed, 2386 insertions(+), 2 deletions(-) > create mode 100644 drivers/ddr/altera/sdram_n5x.c >
Reviewed-by: Ley Foon Tan <[email protected]> Regards Ley Foon
