Dear Kumar, In message <[email protected]> you wrote: > > Hmm, how about dumping all of the LBC registers and comparing > before/after this change.
After the change (here with 2010.09-00558-g79e6313): Board: TQM8555, serial# ABC0555 casl=25 I2C: ready DRAM: 128 MiB FLASH: 128 MiB L2: 256 KB already enabled => fli Bank # 1: CFI conformant FLASH (32 x 16) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E Erase timeout: 16384 ms, write timeout: 1 ms Buffer write timeout: 5 ms, buffer size: 32 bytes Sector Start Addresses: F8000000 E F8020000 E F8040000 E F8060000 E F8080000 E F80A0000 E F80C0000 E F80E0000 E F8100000 E F8120000 E ... FBF20000 E FBF40000 FBF60000 E FBF80000 FBFA0000 FBFC0000 FBFE0000 Bank # 2: CFI conformant FLASH (128 x 128) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E Erase timeout: 16384 ms, write timeout: 1 ms Buffer write timeout: 5 ms, buffer size: 32 bytes Sector Start Addresses: FC000000 FC020000 FC040000 FC060000 FC080000 FC0A0000 FC0C0000 FC0E0000 FC100000 FC120000 ... FFF20000 FFF40000 RO FFF60000 RO FFF80000 RO FFFA0000 RO FFFC0000 RO FFFE0000 RO ccsrbar : 0x000e0000 917504 altcbar : 0x00000000 0 altcsr : 0x00000000 0 bptr : 0x00000000 0 lawbar0 : 0x00000000 0 lawar0 : 0x80f0001e -2131754978 lawbar1 : 0x00080000 524288 lawar1 : 0x8000001c -2147483620 lawbar2 : 0x000f8000 1015808 lawar2 : 0x8040001a -2143289318 lawbar3 : 0x000e2000 925696 lawar3 : 0x80000017 -2147483625 lawbar4 : 0x000c0000 786432 lawar4 : 0x80c0001c -2134900708 lawbar5 : 0x00000000 0 lawar5 : 0x00000000 0 lawbar6 : 0x00000000 0 lawsa6 : 0x00000000 0 lawbar7 : 0x00000000 0 lawsa7 : 0x00000000 0 br0 : 0xf8001801 -134211583 br1 : 0xf8001801 -134211583 br2 : 0x00000000 0 br3 : 0x00000000 0 br4 : 0x00000000 0 br5 : 0x00000000 0 br6 : 0x00000000 0 br7 : 0x00000000 0 or0 : 0xfc000040 -67108800 or1 : 0xfc000040 -67108800 or2 : 0x00000000 0 or3 : 0x00000000 0 or4 : 0x00000000 0 or5 : 0x00000000 0 or6 : 0x00000000 0 or7 : 0x00000000 0 before (here with v2010.06): Board: TQM8555, serial# ABC0555 casl=25 I2C: ready DRAM: 128 MiB FLASH: 128 MiB L2: 256 KB enabled => fli Bank # 1: CFI conformant FLASH (32 x 16) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E Erase timeout: 16384 ms, write timeout: 1 ms Buffer write timeout: 5 ms, buffer size: 32 bytes Sector Start Addresses: F8000000 E F8020000 E F8040000 E F8060000 E F8080000 E F80A0000 E F80C0000 E F80E0000 E F8100000 E F8120000 E ... FBF20000 E FBF40000 E FBF60000 E FBF80000 E FBFA0000 E FBFC0000 E FBFE0000 E Bank # 2: CFI conformant FLASH (32 x 16) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E Erase timeout: 16384 ms, write timeout: 1 ms Buffer write timeout: 5 ms, buffer size: 32 bytes Sector Start Addresses: FC000000 E FC020000 E FC040000 E FC060000 E FC080000 E FC0A0000 E FC0C0000 E FC0E0000 E FC100000 E FC120000 E ... FFF20000 E FFF40000 RO FFF60000 E RO FFF80000 RO FFFA0000 RO FFFC0000 RO FFFE0000 RO ccsrbar : 0x000e0000 917504 altcbar : 0x00000000 0 altcsr : 0x00000000 0 bptr : 0x00000000 0 lawbar0 : 0x00000000 0 lawar0 : 0x80f0001e -2131754978 lawbar1 : 0x00080000 524288 lawar1 : 0x8000001c -2147483620 lawbar2 : 0x000f8000 1015808 lawar2 : 0x8040001a -2143289318 lawbar3 : 0x000e2000 925696 lawar3 : 0x80000017 -2147483625 lawbar4 : 0x000c0000 786432 lawar4 : 0x80c0001c -2134900708 lawbar5 : 0x00000000 0 lawar5 : 0x00000000 0 lawbar6 : 0x00000000 0 lawsa6 : 0x00000000 0 lawbar7 : 0x00000000 0 lawsa7 : 0x00000000 0 br0 : 0xfc001801 -67102719 br1 : 0xf8001801 -134211583 br2 : 0x00000000 0 br3 : 0x00000000 0 br4 : 0x00000000 0 br5 : 0x00000000 0 br6 : 0x00000000 0 br7 : 0x00000000 0 or0 : 0xfc000040 -67108800 or1 : 0xfc000040 -67108800 or2 : 0x00000000 0 or3 : 0x00000000 0 or4 : 0x00000000 0 or5 : 0x00000000 0 or6 : 0x00000000 0 or7 : 0x00000000 0 The problem is obviously BR0: is should be at 0xFC000000, but is actually at 0xF8000000. The problem is that I don't see how this happens. We have the situation with two flash banks, and I verified that we have flashstart = 0xF8000000 in both cases. Hm... I just notice that where we used to see a CPU: 8555E, Version: 1.1, (0x80790011) Core: E500, Version: 2.0, (0x80200020) we now see CPU: 8555E, Version: 1.1, (0x80790011) Core: Unknown, Version: 2.0, (0x80200020) Argh... Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected] Q: Do you know what the death rate around here is? A: One per person. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
