Hi Ashok On 7/27/21 2:36 PM, Ashok Reddy Soma wrote: > Currently xilinx sdhci driver is using zynqmp_mmio_write() to set > tapdelay values. Use xilinx_pm_request() using appropriate arguments > to set input/output tapdelays for zynqmp. Where tapdelay setting is > done by firmware. Host driver should explicitly request DLL reset > before ITAP (assert DLL) and after OTAP (release DLL) to avoid issues > in some cases. Also handle error return where possible. > > Signed-off-by: T Karthik Reddy <[email protected]> > Signed-off-by: Ashok Reddy Soma <[email protected]> > --- > > Changes in v2: > - Added comment for why 1ms delay is needed between DLL assert and > release > - Remove mmc->dev->seq_ and use priv->deviceid instead > > board/xilinx/zynqmp/tap_delays.c | 89 +++----------------------------- > drivers/mmc/zynq_sdhci.c | 75 ++++++++++++++++++++++----- > include/zynqmp_tap_delay.h | 25 ++++++--- > 3 files changed, 87 insertions(+), 102 deletions(-) > > diff --git a/board/xilinx/zynqmp/tap_delays.c > b/board/xilinx/zynqmp/tap_delays.c > index d16bbb8eff..4ce2244060 100644 > --- a/board/xilinx/zynqmp/tap_delays.c > +++ b/board/xilinx/zynqmp/tap_delays.c > @@ -10,92 +10,17 @@ > #include <asm/arch/sys_proto.h> > #include <linux/delay.h> > #include <mmc.h> > +#include <zynqmp_firmware.h> > > -#define SD_DLL_CTRL 0xFF180358 > -#define SD_ITAP_DLY 0xFF180314 > -#define SD_OTAP_DLY 0xFF180318 > -#define SD0_DLL_RST_MASK 0x00000004 > -#define SD0_DLL_RST 0x00000004 > -#define SD1_DLL_RST_MASK 0x00040000 > -#define SD1_DLL_RST 0x00040000 > -#define SD0_ITAPCHGWIN_MASK 0x00000200 > -#define SD0_ITAPCHGWIN 0x00000200 > -#define SD1_ITAPCHGWIN_MASK 0x02000000 > -#define SD1_ITAPCHGWIN 0x02000000 > -#define SD0_ITAPDLYENA_MASK 0x00000100 > -#define SD0_ITAPDLYENA 0x00000100 > -#define SD1_ITAPDLYENA_MASK 0x01000000 > -#define SD1_ITAPDLYENA 0x01000000 > -#define SD0_ITAPDLYSEL_MASK 0x000000FF > -#define SD1_ITAPDLYSEL_MASK 0x00FF0000 > -#define SD0_OTAPDLYSEL_MASK 0x0000003F > -#define SD1_OTAPDLYSEL_MASK 0x003F0000 > - > -void zynqmp_dll_reset(u8 deviceid) > +int arasan_zynqmp_set_in_tapdelay(u8 deviceid, u32 type, u32 itap_delay) > { > - /* Issue DLL Reset */ > - if (deviceid == 0) > - zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, > - SD0_DLL_RST); > - else > - zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, > - SD1_DLL_RST); > - > - mdelay(1); > > - /* Release DLL Reset */ > - if (deviceid == 0) > - zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0); > - else > - zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0); > + return xilinx_pm_request(PM_IOCTL, (u32)deviceid, IOCTL_SET_SD_TAPDELAY, > + type, itap_delay, NULL);
I have tried to apply these patches to latest tree and this breaks SPL flow because IOCTL_SET_SD_TAPDELAY in TF-A is doing much more steps then just single write. It means for SPL case we have to implement that steps in xilinx_pm_request() as it is done for PM_FPGA_LOAD case. Thanks, Michal
