> From: Zong Li <zong...@sifive.com> > Sent: Wednesday, September 01, 2021 3:02 PM > To: Rick Jian-Zhi Chen(陳建志) <r...@andestech.com>; Leo Yu-Chi Liang(梁育齊) > <ycli...@andestech.com>; bmeng...@gmail.com; sean...@gmail.com; > green....@sifive.com; paul.walms...@sifive.com; s...@chromium.org; > u-boot@lists.denx.de > Cc: Zong Li <zong...@sifive.com> > Subject: [PATCH v5 2/5] common: board_r: support enable_caches for RISC-V > > The enable_caches is a generic hook for architecture-implemented, we leverage > this function to enable caches for RISC-V > > Signed-off-by: Zong Li <zong...@sifive.com> > --- > arch/riscv/lib/cache.c | 4 ++++ > common/board_r.c | 4 ++-- > 2 files changed, 6 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen <r...@andestech.com>
