On Fri, 8 Oct 2021 at 04:01, Nico Cheng <[email protected]> wrote: > > We configured the drive strength and security of EMMC in > arch_cpu_init().
Could you point me to a public version of the TRM (and ideally also of the datasheet), so I can review this series? Thanks, Philipp. > > Signed-off-by: Nico Cheng <[email protected]> > --- > > arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c > b/arch/arm/mach-rockchip/rk3568/rk3568.c > index 973b4f9dcb..3f9a435c3c 100644 > --- a/arch/arm/mach-rockchip/rk3568/rk3568.c > +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c > @@ -13,6 +13,14 @@ > > #define PMUGRF_BASE 0xfdc20000 > #define GRF_BASE 0xfdc60000 > +#define GRF_GPIO1B_DS_2 0x218 > +#define GRF_GPIO1B_DS_3 0x21c > +#define GRF_GPIO1C_DS_0 0x220 > +#define GRF_GPIO1C_DS_1 0x224 > +#define GRF_GPIO1C_DS_2 0x228 > +#define GRF_GPIO1C_DS_3 0x22c > +#define SGRF_BASE 0xFDD18000 > +#define SGRF_SOC_CON4 0x10 > > /* PMU_GRF_GPIO0D_IOMUX_L */ > enum { > @@ -81,5 +89,16 @@ void board_debug_uart_init(void) > > int arch_cpu_init(void) > { > +#ifdef CONFIG_SPL_BUILD > + /* Set the emmc sdmmc0 to secure */ > + writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4); > + /* set the emmc ds to level 2 */ > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); > +#endif > return 0; > } > -- > 2.17.1 >
