On Wed, 20 Oct 2021 at 02:50, Chia-Wei Wang <chiawei_w...@aspeedtech.com> wrote:
>
> Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine
> of ASPEED AST2600 SoCs.
>
> As ACRY and HACE share the same reset control bit, we do not
> perform the reset-hold-n-release operation during their clock
> ungating process. Instead, only reset release is conducted to
> prevent mutual interference.
Is this okay to do? If so, can we do this for other clocks without
having to wait 100us?
It would make sense to merge this patch with the HACE patch to avoid
adding and then removing code in the same series.
>
> Signed-off-by: Chia-Wei Wang <chiawei_w...@aspeedtech.com>
> ---
> .../arm/include/asm/arch-aspeed/scu_ast2600.h | 1 +
> drivers/clk/aspeed/clk_ast2600.c | 22 +++++++++++++++++--
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
> b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
> index d7b500f656..7c5aab98b6 100644
> --- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
> +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
> @@ -8,6 +8,7 @@
> #define SCU_UNLOCK_KEY 0x1688a8a8
>
> #define SCU_CLKGATE1_EMMC BIT(27)
> +#define SCU_CLKGATE1_ACRY BIT(24)
> #define SCU_CLKGATE1_MAC2 BIT(21)
> #define SCU_CLKGATE1_MAC1 BIT(20)
> #define SCU_CLKGATE1_USB_HUB BIT(14)
> diff --git a/drivers/clk/aspeed/clk_ast2600.c
> b/drivers/clk/aspeed/clk_ast2600.c
> index 69128fd3c4..f6ebf824aa 100644
> --- a/drivers/clk/aspeed/clk_ast2600.c
> +++ b/drivers/clk/aspeed/clk_ast2600.c
> @@ -1018,11 +1018,26 @@ static ulong ast2600_enable_haceclk(struct
> ast2600_scu *scu)
> uint32_t reset_bit;
> uint32_t clkgate_bit;
>
> + /* share the same reset control bit with ACRY */
> reset_bit = BIT(ASPEED_RESET_HACE);
> clkgate_bit = SCU_CLKGATE1_HACE;
>
> - writel(reset_bit, &scu->modrst_ctrl1);
> - udelay(100);
> + writel(clkgate_bit, &scu->clkgate_clr1);
> + mdelay(20);
> + writel(reset_bit, &scu->modrst_clr1);
> +
> + return 0;
> +}
> +
> +static ulong ast2600_enable_rsaclk(struct ast2600_scu *scu)
> +{
> + uint32_t reset_bit;
> + uint32_t clkgate_bit;
> +
> + /* share the same reset control bit with HACE */
> + reset_bit = BIT(ASPEED_RESET_HACE);
> + clkgate_bit = SCU_CLKGATE1_ACRY;
> +
> writel(clkgate_bit, &scu->clkgate_clr1);
> mdelay(20);
> writel(reset_bit, &scu->modrst_clr1);
> @@ -1071,6 +1086,9 @@ static int ast2600_clk_enable(struct clk *clk)
> case ASPEED_CLK_GATE_YCLK:
> ast2600_enable_haceclk(priv->scu);
> break;
> + case ASPEED_CLK_GATE_RSACLK:
> + ast2600_enable_rsaclk(priv->scu);
> + break;
> default:
> pr_err("can't enable clk\n");
> return -ENOENT;
> --
> 2.17.1
>
