On 12.10.21 13:19, Pali Rohár wrote:
PCI Bridge which represents Aardvark PCIe Root Port does not have
configurable bars.
So ensure that write operation to bars registers on PCI Bridge is noop and
bars registers always contain zero address which indicates that bars are
unsupported.
After this change U-Boot 'pci bar 0.0.0' command does not show any
allocated bars for PCI Bridge device.
Signed-off-by: Pali Rohár <[email protected]>
Fixes: cb056005dc67 ("arm: a37xx: pci: Add support for accessing PCI Bridge on root
bus")
Applied to u-boot-marvell/master
Thanks,
Stefan
---
drivers/pci/pci-aardvark.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 38eff495ab1c..ade5ab056f84 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -581,6 +581,10 @@ static int pcie_advk_write_config(struct udevice *bus,
pci_dev_t bdf,
if (offset >= 0x10 && offset < 0x34) {
data = pcie->cfgcache[(offset - 0x10) / 4];
data = pci_conv_size_to_32(data, value, offset, size);
+ /* This PCI bridge does not have configurable bars */
+ if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
+ (offset & ~3) == PCI_BASE_ADDRESS_1)
+ data = 0x0;
pcie->cfgcache[(offset - 0x10) / 4] = data;
} else if ((offset & ~3) == PCI_ROM_ADDRESS1) {
data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
Viele Grüße,
Stefan
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