Accept a bloblist and control devicetree from a previous phase in
registers r0 and r1

Signed-off-by: Simon Glass <s...@chromium.org>
---

 arch/arm/cpu/armv7/start.S | 7 ++++++-
 arch/arm/lib/crt0.S        | 4 ++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 698e15b8e18..5ebe2c26693 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -36,6 +36,10 @@
 #endif
 
 reset:
+       # Keep passage information in case it is provided
+       mov     r6, r0
+       mov     r7, r1
+
        /* Allow the board to save important registers */
        b       save_boot_params
 save_boot_params_ret:
@@ -124,7 +128,8 @@ switch_to_hypervisor_ret:
        bl      cpu_init_crit
 #endif
 #endif
-
+       # Note: r6 and r7 are available to _main in case standard passage is
+       # used
        bl      _main
 
 
/*------------------------------------------------------------------------------*/
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 956d258c9da..f5343b22683 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -113,6 +113,10 @@ ENTRY(_main)
        CLEAR_BSS
 #endif
 
+#if CONFIG_IS_ENABLED(PASSAGE_IN)
+       str     r6, [r9, GD_PASSAGE_BLOBLIST]
+       str     r7, [r9, GD_PASSAGE_DTB_OFF]
+#endif
        mov     r0, #0
        bl      board_init_f
 
-- 
2.33.1.1089.g2158813163f-goog

Reply via email to