On 11/11/2010 12:37 PM, Xiangfu Liu wrote:
> From: Xiangfu Liu <xian...@sharism.cc>
If possible, please describe what Jz4740 SoC is, an overview of JzRISC
processor, where this patch is from or where to get the original work,
and so on.
It also would be nice we could have Signed-off-by: or Acked-by: from
Ingenic people, as some files contains Ingenic copyright statements.
Please consider.
> diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk
> new file mode 100644
> index 0000000..f43f53b
> --- /dev/null
> +++ b/arch/mips/cpu/xburst/config.mk
> @@ -0,0 +1,33 @@
> +#
> +# (C) Copyright 2003
> +# Wolfgang Denk, DENX Software Engineering, <w...@denx.de>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' |
> cut -d. -f2)
> +MIPSFLAGS:=$(shell \
> +if [ "$v" -lt "14" ]; then \
> + echo "-mcpu=4kc"; \
> +else \
> + echo "-march=4kc -mtune=4kc"; \
> +fi)
> +
> +MIPSFLAGS += $(ENDIANNESS) -mabicalls -mips32
ENDIANNESS looks unused. Jz47xx series are little endian SoCs, then
let's remove it.
> +PLATFORM_CPPFLAGS += $(MIPSFLAGS)
> diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
> new file mode 100644
> index 0000000..682debf
> --- /dev/null
> +++ b/arch/mips/cpu/xburst/cpu.c
> @@ -0,0 +1,158 @@
[snip]
> +void flush_icache_all(void)
> +{
> + u32 addr, t = 0;
> +
> + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
> + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
> +
> + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
> + addr += CONFIG_SYS_CACHELINE_SIZE) {
> + cache_op(Index_Store_Tag_I, addr);
> + }
> +
> + /* invalidate btb */
> + asm volatile (
> + ".set mips32\n\t"
> + "mfc0 %0, $16, 7\n\t"
> + "nop\n\t"
> + "ori %0,2\n\t"
> + "mtc0 %0, $16, 7\n\t"
> + ".set mips2\n\t"
> + :
> + : "r" (t));
> +}
As pointed out before, incorrect use of assembler control. Why set
mips32 without pushing the current control info, and why set it back
to mips2? 'noreorder' is also missing here.
asm volatile (
".set push\n\t"
".set noreorder\n\t"
".set mips32\n\t"
"mfc0 %0, $16, 7\n\t"
"nop\n\t"
"ori %0, 2\n\t"
"mtc0 %0, $16, 7\n\t"
".set pop\n\t"
:
: "r" (t));
Hmm?
> +void flush_dcache_all(void)
> +{
> + u32 addr;
> +
> + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
> + addr += CONFIG_SYS_CACHELINE_SIZE) {
> + cache_op(Index_Writeback_Inv_D, addr);
> + }
> +
> + asm volatile ("sync");
> +}
> +
> +void flush_cache_all(void)
> +{
> + flush_dcache_all();
> + flush_icache_all();
> +}
> diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
> new file mode 100644
> index 0000000..b8e9a15
> --- /dev/null
> +++ b/arch/mips/cpu/xburst/jz4740.c
I couldn't mention about its validity of the following DRAM init code
from the technically POV. As long as it works for you, I'm ok. Most
of the code looks well-written conforming to the coding styles. A few
trivial cleanups, please.
> @@ -0,0 +1,257 @@
> +/*
> + * Jz4740 common routines
> + *
> + * Copyright (c) 2006
> + * Ingenic Semiconductor, <jl...@ingenic.cn>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +
> +#include <asm/jz4740.h>
> +
> +/* PLL output clock = EXTAL * NF / (NR * NO)
> + *
> + * NF = FD + 2, NR = RD + 2
> + * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
> + */
> +void pll_init(void)
> +{
> + register unsigned int cfcr, plcr1;
> + int n2FR[33] = {
> + 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
> + 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
> + 9
> + };
> + int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
> + int nf, pllout2;
> +
> + cfcr = CPM_CPCCR_CLKOEN |
> + CPM_CPCCR_PCS |
> + (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
> + (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
> + (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
> + (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
> + (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
> +
> + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED :
> (CONFIG_SYS_CPU_SPEED / 2);
pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED :
(CONFIG_SYS_CPU_SPEED / 2);
> + /* Init USB Host clock, pllout2 must be n*48MHz */
> + REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
> +
> + nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
> + plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
> + (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
> + (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
> + (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
> + CPM_CPPCR_PLLEN; /* enable PLL */
> +
> + /* init PLL */
> + REG_CPM_CPCCR = cfcr;
> + REG_CPM_CPPCR = plcr1;
> +}
> +
> +void sdram_init(void)
> +{
> + register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
> +
> + unsigned int cas_latency_sdmr[2] = {
> + EMC_SDMR_CAS_2,
> + EMC_SDMR_CAS_3,
> + };
> +
> + unsigned int cas_latency_dmcr[2] = {
> + 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
> + 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
> + };
> +
> + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
> +
> + cpu_clk = CONFIG_SYS_CPU_SPEED;
> + mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
> +
> + REG_EMC_BCR = 0; /* Disable bus release */
> + REG_EMC_RTCSR = 0; /* Disable clock for counting */
> +
> + /* Fault DMCR value for mode register setting*/
> +#define SDRAM_ROW0 11
> +#define SDRAM_COL0 8
> +#define SDRAM_BANK40 0
> +
> + dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
> + ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
> + (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
> + (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
> + EMC_DMCR_EPIN |
> + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
Unless it breaks 80-charcter-wide rule, please provide whitespaces at
proper places.
dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
(SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
EMC_DMCR_EPIN |
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
> + /* Basic DMCR value */
> + dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
> + ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
> + (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
> + (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
> + EMC_DMCR_EPIN |
> + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
Ditto.
> + /* SDRAM timimg */
> + ns = 1000000000 / mem_clk;
> + tmp = SDRAM_TRAS/ns;
> + if (tmp < 4) tmp = 4;
> + if (tmp > 11) tmp = 11;
> + dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
> + tmp = SDRAM_RCD/ns;
> + if (tmp > 3) tmp = 3;
> + dmcr |= (tmp << EMC_DMCR_RCD_BIT);
> + tmp = SDRAM_TPC/ns;
> + if (tmp > 7) tmp = 7;
> + dmcr |= (tmp << EMC_DMCR_TPC_BIT);
> + tmp = SDRAM_TRWL/ns;
> + if (tmp > 3) tmp = 3;
> + dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
> + tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
> + if (tmp > 14) tmp = 14;
> + dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
> +
> + /* SDRAM mode value */
> + sdmode = EMC_SDMR_BT_SEQ |
> + EMC_SDMR_OM_NORMAL |
> + EMC_SDMR_BL_4 |
> + cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
> +
> + /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
> + REG_EMC_DMCR = dmcr;
> + REG8(EMC_SDMR0|sdmode) = 0;
REG8(EMC_SDMR0 | sdmode) = 0;
> + /* Wait for precharge, > 200us */
> + tmp = (cpu_clk / 1000000) * 1000;
> + while (tmp--);
> +
> + /* Stage 2. Enable auto-refresh */
> + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
> +
> + tmp = SDRAM_TREF/ns;
> + tmp = tmp/64 + 1;
> + if (tmp > 0xff) tmp = 0xff;
> + REG_EMC_RTCOR = tmp;
> + REG_EMC_RTCNT = 0;
> + REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
> +
> + /* Wait for number of auto-refresh cycles */
> + tmp = (cpu_clk / 1000000) * 1000;
> + while (tmp--);
> +
> + /* Stage 3. Mode Register Set */
> + REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
> + REG8(EMC_SDMR0|sdmode) = 0;
REG8(EMC_SDMR0 | sdmode) = 0;
> + /* Set back to basic DMCR value */
> + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
> +
> + /* everything is ok now */
> +}
> +
> +#ifndef CONFIG_NAND_SPL
> +
> +static void calc_clocks(void)
> +{
> + DECLARE_GLOBAL_DATA_PTR;
> +
> + unsigned int pllout;
> + unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
> +
> + pllout = __cpm_get_pllout();
> +
> + gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
> + gd->sys_clk = pllout / div[__cpm_get_hdiv()];
> + gd->per_clk = pllout / div[__cpm_get_pdiv()];
> + gd->mem_clk = pllout / div[__cpm_get_mdiv()];
> + gd->dev_clk = CONFIG_SYS_EXTAL;
> +}
> +
> +static void rtc_init(void)
> +{
> + while ( !__rtc_write_ready()) ;
> + __rtc_enable_alarm(); /* enable alarm */
> +
> + while ( !__rtc_write_ready())
> + ;
> + REG_RTC_RGR = 0x00007fff; /* type value */
> +
> + while ( !__rtc_write_ready())
> + ;
> + REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
> +
> + while ( !__rtc_write_ready())
> + ;
> + REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
> +#if 0
> + unsigned long rtcsta;
> +
> + while ( !__rtc_write_ready())
> + ;
> + rtcsta = REG_RTC_HWRSR;
> + while ( !__rtc_write_ready())
> + ;
> + if (rtcsta & 0x33) {
> + if (rtcsta & 0x10) {
> + while ( !__rtc_write_ready())
> + ;
> + REG_RTC_RSR = 0x0;
> + }
> + while ( !__rtc_write_ready())
> + ;
> + REG_RTC_HWRSR = 0x0;
> + }
> +#endif
Get rid of unused #if 0 code.
> +}
> +
> +/* U-Boot common routines */
> +phys_size_t initdram(int board_type)
> +{
> + u32 dmcr;
> + u32 rows, cols, dw, banks;
> + ulong size;
> +
> + dmcr = REG_EMC_DMCR;
> + rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
> + cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
> + dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
> + banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
> +
> + size = (1 << (rows + cols)) * dw * banks;
> +
> + return size;
> +}
> +
> +/*
> + * jz4740 board init routine
> + */
> +extern void board_early_init(void);
> +int jz_board_init(void)
> +{
> + board_early_init(); /* init gpio, pll etc. */
> +#ifndef CONFIG_NAND_U_BOOT
> + pll_init(); /* init PLL */
> + sdram_init(); /* init sdram memory */
> +#endif
> + calc_clocks(); /* calc the clocks */
> + rtc_init(); /* init rtc on any reset: */
> + return 0;
> +}
> +
> +#endif /* CONFIG_NAND_SPL */
Inconsistent comment indentations. Use tabs, not spaces.
> diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
> new file mode 100644
> index 0000000..b05cc67
> --- /dev/null
> +++ b/arch/mips/cpu/xburst/start.S
> @@ -0,0 +1,165 @@
> +/*
> + * Startup Code for MIPS32 XBURST CPU-core
> + *
> + * Copyright (c) 2010 Xiangfu Liu <xian...@sharism.cc>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +#include <asm/regdef.h>
> +#include <asm/mipsregs.h>
> +#include <asm/addrspace.h>
> +#include <asm/cacheops.h>
> +
> +#include <asm/jz4740.h>
> +
> + .set noreorder
> +
> + .globl _start
> + .text
> +_start:
> + /* Initialize GOT pointer.
> + */
> + bal 1f
> + nop
> + .word _GLOBAL_OFFSET_TABLE_
> +1:
> + lw gp, 0(ra)
> + li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
> +
> + la t9, board_init_f
> + jr t9
> + nop
> +
> +/*
> + * void relocate_code (addr_sp, gd, addr_moni)
> + *
> + * This "function" does not return, instead it continues in RAM
> + * after relocating the monitor code.
> + *
> + * a0 = addr_sp
> + * a1 = gd
> + * a2 = destination address
> + */
> + .globl relocate_code
> + .ent relocate_code
> +relocate_code:
> + move sp, a0 /* Set new stack pointer */
> +
> + li t0, TEXT_BASE
> + la t3, in_ram
> + lw t2, -12(t3) /* t2 <-- uboot_end_data */
> + move t1, a2
> +
> + /*
> + * Fix GOT pointer:
> + *
> + * New GOT-PTR = (old GOT-PTR - TEXT_BASE) + Destination Address
> + */
> + move t6, gp
> + sub gp, TEXT_BASE
> + add gp, a2 /* gp now adjusted */
> + sub t6, gp, t6 /* t6 <-- relocation offset*/
> +
> + /*
> + * t0 = source address
> + * t1 = target address
> + * t2 = source end address
> + */
> +1:
> + lw t3, 0(t0)
> + sw t3, 0(t1)
> + addu t0, 4
> + ble t0, t2, 1b
> + addu t1, 4 /* delay slot */
> +
> + /* If caches were enabled, we would have to flush them here.
> + * flush d-cache */
> + .set push
.Set push is expected to be followed by assembler control change(s).
In this case, you probably want to set mips3 for CACHE instruction.
> + li t0, KSEG0
> + addi t1, t0, CONFIG_SYS_DCACHE_SIZE
> +2:
> + cache Index_Writeback_Inv_D, 0(t0)
> + bne t0, t1, 2b
> + addi t0, CONFIG_SYS_CACHELINE_SIZE
> +
> + sync
> +
> + /* flush i-cache */
> + li t0, KSEG0
> + addi t1, t0, CONFIG_SYS_ICACHE_SIZE
> +3:
> + cache Index_Invalidate_I, 0(t0)
> + bne t0, t1, 3b
> + addi t0, CONFIG_SYS_CACHELINE_SIZE
> +
> + /* Invalidate BTB */
> + mfc0 t0, CP0_CONFIG, 7
> + nop
> + ori t0, 2
> + mtc0 t0, CP0_CONFIG, 7
> + nop
> +
> + .set pop
> +
> + /* Jump to where we've relocated ourselves.
> + */
> + addi t0, a2, in_ram - _start
> + j t0
> + nop
Use JR, not J.
> + .word uboot_end_data
> + .word uboot_end
> + .word num_got_entries
> +
> +in_ram:
> + /* Now we want to update GOT */
> + lw t3, -4(t0) /* t3 <-- num_got_entries */
> + addi t4, gp, 8 /* Skipping first two entries. */
> + li t2, 2
> +1:
> + lw t1, 0(t4)
> + beqz t1, 2f
> + add t1, t6
> + sw t1, 0(t4)
> +2:
> + addi t2, 1
> + blt t2, t3, 1b
> + addi t4, 4 /* delay slot */
> +
> + /* Clear BSS */
> + lw t1, -12(t0) /* t1 <-- uboot_end_data */
> + lw t2, -8(t0) /* t2 <-- uboot_end */
> + add t1, t6 /* adjust pointers */
> + add t2, t6
> +
> + sub t1, 4
> +1: addi t1, 4
> + bltl t1, t2, 1b
> + sw zero, 0(t1) /* delay slot */
> +
> + move a0, a1
> + la t9, board_init_r
> + j t9
> + move a1, a2 /* delay slot */
Use JR, not J.
> + .end relocate_code
> +
> \ No newline at end of file
I checked the diffs between cpu/start.S and cpu/xburst/start.S. The
relocation code itself looks ok.
> diff --git a/arch/mips/cpu/xburst/start_spl.S
> b/arch/mips/cpu/xburst/start_spl.S
> new file mode 100644
> index 0000000..f775e3a
> --- /dev/null
> +++ b/arch/mips/cpu/xburst/start_spl.S
> @@ -0,0 +1,63 @@
> +/*
> + * Startup Code for MIPS32 XBURST CPU-core
> + *
> + * Copyright (c) 2010 Xiangfu Liu <xian...@sharism.cc>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 3 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +#include <asm/regdef.h>
> +#include <asm/mipsregs.h>
> +#include <asm/addrspace.h>
> +#include <asm/cacheops.h>
> +
> +#include <asm/jz4740.h>
> +
> + .set noreorder
> +
> + .globl _start
> + .text
> +_start:
> + .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
> +reset:
> + /*
> + * STATUS register
> + * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
> + */
> + li t0, 0x0040FC04
> + mtc0 t0, CP0_STATUS
> + /* CAUSE register
> + * IV=1, use the specical interrupt vector (0x200) */
> + li t1, 0x00800000
> + mtc0 t1, CP0_CAUSE
> +
> + bal 1f
> + nop
> + .word _GLOBAL_OFFSET_TABLE_
> +1:
> + move gp, ra
> + lw t1, 0(ra)
> + move gp, t1
These three lines could be written in one-liner:
lw gp, 0(ra)
> + la sp, 0x80004000
> + la t9, nand_boot
> + j t9
> + nop
Use JR, not J.
> diff --git a/arch/mips/cpu/xburst/usbboot.S b/arch/mips/cpu/xburst/usbboot.S
> new file mode 100644
> index 0000000..eb8faa6
> --- /dev/null
> +++ b/arch/mips/cpu/xburst/usbboot.S
I'm going to approve this code as-is, except for coding style issues.
Do not use '//' for comments.
> @@ -0,0 +1,880 @@
> +/*
> + * for jz4740 usb boot
> + *
> + * Copyright (c) 2009 Author: <jl...@ingenic.cn>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> + .set noreorder
> + .globl usb_boot
> + .text
> +
> +//----------------------------------------------------------------------
> +// Both NAND and USB boot load data to D-Cache first, then transfer
> +// data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
> +// So init caches first and then dispatch to a proper boot routine.
> +//----------------------------------------------------------------------
/*
* Both NAND and USB boot load data to D-Cache first, then transfer
* data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
* So init caches first and then dispatch to a proper boot routine.
*/
> +.macro load_addr reg addr
> + li \reg, 0x80000000
> + addiu \reg, \reg, \addr
> + la $2, usbboot_begin
> + subu \reg, \reg, $2
> +.endm
> +
> +usb_boot:
> + //--------------------------------------------------------------
> + // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
> + //--------------------------------------------------------------
> + la $9, 0xB0000000 // CPCCR: Clock Control Register
> + la $8, 0x42041110 // I:S:M:P=1:2:2:2
> + sw $8, 0($9)
usb_boot:
/*
* Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
*/
la $9, 0xB0000000 # CPCCR: Clock Control Register
la $8, 0x42041110 # I:S:M:P=1:2:2:2
sw $8, 0($9)
And so on. With such cleanups, this is ok.
> + la $9, 0xB0000010 // CPPCR: PLL Control Register
> + la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
> + sw $8, 0($9)
> +
> + mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state
> + nop
> +
> + mtc0 $0, $16 // CP0_CONFIG
> + nop
> +
> + // Relocate code to beginning of the ram
> +
> + la $2, usbboot_begin
> + la $3, usbboot_end
> + li $4, 0x80000000
[snip]
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