[Responding here rather than directly to Dave since his e-mail showed up blank here for some reason]
On Mon, 15 Nov 2010 18:30:46 +0100 Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote: > > > > > The experts found an issue within init code and it looks like a proper > > > patch will be added to mainline shortly. > > > The discussion of the proper fix is right in this thread ... > > > > It should be timing issue in the SoC, software did not have a proper > > process to handle > > IMMR registers accessing. > > > > I agree Kumar on this. > > Adding the read back with load is needing for the LAW window changing. > > And something like sync/eieio instruction also need to be added between > > stw and lwz... > > to have a proper order accessing. Wouldn't the fact that you're accessing the same address -- and that it's cache inhibited -- eliminate the need for a sync instruction between the stw and lwz? -Scott _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
