Add clock tables required for bing up ECSPI interfaces
Signed-off-by: Elmar Albert <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: uboot-imx <[email protected]>
Signed-off-by: Elmar Albert <[email protected]>
---
drivers/clk/imx/clk-imx8mp.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index ad84ce38ed..8a374ef0b5 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -160,6 +160,18 @@ static const char *imx8mp_gic_sels[] = {"clock-osc-24m",
"sys_pll2_200m", "sys_p
"sys_pll2_100m", "sys_pll1_800m",
"sys_pll2_500m", "clk_ext4",
"audio_pll2_out" };
+static const char *imx8mp_ecspi1_sels[] = {"clock-osc_24m", "sys_pll2_200m",
"sys_pll1_40m",
+ "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m",
"audio_pll2_out", };
+
+static const char *imx8mp_ecspi2_sels[] = {"clock-osc_24m", "sys_pll2_200m",
"sys_pll1_40m",
+ "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m",
"audio_pll2_out", };
+
+static const char *imx8mp_ecspi3_sels[] = {"clock-osc_24m", "sys_pll2_200m",
"sys_pll1_40m",
+ "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m",
"audio_pll2_out", };
+
static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m",
"sys_pll1_160m",
"vpu_pll_out", "sys_pll2_125m",
"sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m" };
@@ -274,6 +286,9 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3",
imx8mp_uart3_sels, base + 0xb000));
clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4",
imx8mp_uart4_sels, base + 0xb080));
clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic",
imx8mp_gic_sels, base + 0xb200));
+ clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1",
imx8mp_ecspi1_sels, base + 0xb280));
+ clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2",
imx8mp_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3",
imx8mp_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels,
base + 0xb900));
clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3",
imx8mp_usdhc3_sels, base + 0xbc80));
@@ -282,7 +297,9 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base +
0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels),
CLK_IS_CRITICAL));
clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk",
"dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
-
+ clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk",
"ecspi1", base + 0x4070, 0));
+ clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4("ecspi2_root_clk",
"ecspi2", base + 0x4080, 0));
+ clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4("ecspi3_root_clk",
"ecspi3", base + 0x4090, 0));
clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk",
"enet_axi", base + 0x40a0, 0));
clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk",
"ipg_root", base + 0x40b0, 0));
clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk",
"ipg_root", base + 0x40c0, 0));
--
2.25.1
