On Fri, Apr 1, 2022 at 7:55 AM Marek Vasut <[email protected]> wrote: > > Add DT bindings for a subset of GPCv2 which handles USB and PCIe PDs, > HSIOMIX PD controller and missing USB PD properties. This is required > to bring up the DWC3 USB controller up. > > This is based on linux next and patches which are still pending > review, but which are likely going to be part of Linux 5.19: > b2d67d7bdf74 ("arm64: dts: imx8mp: disable usb3_phy1") > 290918c72a29 ("arm64: dts: imx8mp: Add memory for USB3 glue layer to usb3 > nodes") > https://www.spinics.net/lists/arm-kernel/msg958501.html > > Signed-off-by: Marek Vasut <[email protected]> > Cc: Fabio Estevam <[email protected]> > Cc: Peng Fan <[email protected]> > Cc: Stefano Babic <[email protected]> > --- > arch/arm/dts/imx8mp.dtsi | 72 ++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 70 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi > index f9d64253c8a..79b65750da9 100644 > --- a/arch/arm/dts/imx8mp.dtsi > +++ b/arch/arm/dts/imx8mp.dtsi > @@ -4,6 +4,7 @@ > */ > > #include <dt-bindings/clock/imx8mp-clock.h> > +#include <dt-bindings/power/imx8mp-power.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/input.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > @@ -434,6 +435,44 @@ > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > #reset-cells = <1>; > }; > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mp-gpc"; > + reg = <0x303a0000 0x1000>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #interrupt-cells = <3>; > + > + pgc { > + #address-cells = <1>; > + #size-cells = <0>; > + > + pgc_pcie_phy: power-domain@1 { > + #power-domain-cells = <0>; > + reg = > <IMX8MP_POWER_DOMAIN_PCIE_PHY>; > + }; > + > + pgc_usb1_phy: power-domain@2 { > + #power-domain-cells = <0>; > + reg = > <IMX8MP_POWER_DOMAIN_USB1_PHY>; > + }; > + > + pgc_usb2_phy: power-domain@3 { > + #power-domain-cells = <0>; > + reg = > <IMX8MP_POWER_DOMAIN_USB2_PHY>; > + }; > + > + pgc_hsiomix: power-domains@17 { > + #power-domain-cells = <0>; > + reg = > <IMX8MP_POWER_DOMAIN_HSIOMIX>; > + clocks = <&clk > IMX8MP_CLK_HSIO_AXI>, > + <&clk > IMX8MP_CLK_HSIO_ROOT>; > + assigned-clocks = <&clk > IMX8MP_CLK_HSIO_AXI>; > + assigned-clock-parents = > <&clk IMX8MP_SYS_PLL2_500M>; > + assigned-clock-rates = > <500000000>; > + }; > + }; > + }; > }; > > aips2: bus@30400000 { > @@ -842,6 +881,28 @@ > }; > }; > > + aips4: bus@32c00000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + reg = <0x32c00000 0x400000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + hsio_blk_ctrl: blk-ctrl@32f10000 { > + compatible = "fsl,imx8mp-hsio-blk-ctrl", > "syscon"; > + reg = <0x32f10000 0x24>; > + clocks = <&clk IMX8MP_CLK_USB_ROOT>, > + <&clk IMX8MP_CLK_PCIE_ROOT>; > + clock-names = "usb", "pcie"; > + power-domains = <&pgc_hsiomix>, > <&pgc_hsiomix>, > + <&pgc_usb1_phy>, > <&pgc_usb2_phy>, > + <&pgc_hsiomix>, > <&pgc_pcie_phy>; > + power-domain-names = "bus", "usb", "usb-phy1", > + "usb-phy2", "pcie", > "pcie-phy"; > + #power-domain-cells = <1>; > + }; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, > @@ -865,17 +926,20 @@ > clock-names = "phy"; > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; > assigned-clock-parents = <&clk IMX8MP_CLK_24M>; > + power-domains = <&hsio_blk_ctrl > IMX8MP_HSIOBLK_PD_USB_PHY1>; > #phy-cells = <0>; > status = "disabled"; > }; > > usb3_0: usb@32f10100 { > compatible = "fsl,imx8mp-dwc3"; > - reg = <0x32f10100 0x8>; > + reg = <0x32f10100 0x8>, > + <0x381f0000 0x20>; > clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > <&clk IMX8MP_CLK_USB_ROOT>; > clock-names = "hsio", "suspend"; > interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&hsio_blk_ctrl > IMX8MP_HSIOBLK_PD_USB>; > #address-cells = <1>; > #size-cells = <1>; > dma-ranges = <0x40000000 0x40000000 0xc0000000>; > @@ -907,16 +971,20 @@ > clock-names = "phy"; > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; > assigned-clock-parents = <&clk IMX8MP_CLK_24M>; > + power-domains = <&hsio_blk_ctrl > IMX8MP_HSIOBLK_PD_USB_PHY2>; > #phy-cells = <0>; > + status = "disabled"; > }; > > usb3_1: usb@32f10108 { > compatible = "fsl,imx8mp-dwc3"; > - reg = <0x32f10108 0x8>; > + reg = <0x32f10108 0x8>, > + <0x382f0000 0x20>; > clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > <&clk IMX8MP_CLK_USB_ROOT>; > clock-names = "hsio", "suspend"; > interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&hsio_blk_ctrl > IMX8MP_HSIOBLK_PD_USB>; > #address-cells = <1>; > #size-cells = <1>; > dma-ranges = <0x40000000 0x40000000 0xc0000000>; > -- > 2.35.1 >
Thanks for working on this! This helps get DWC3 USB working on IMX8MP. Tested-By: Tim Harvey <[email protected]> #imx8mp-venice-gw74xx Best Regards, Tim
