Hi Michal, On Tue, Jun 7, 2022 at 3:47 PM Michal Simek <michal.si...@xilinx.com> wrote: > > Hi, > > On 6/7/22 13:37, Oleksandr Suvorov wrote: > > Hi Michal, > > > > On Tue, Jun 7, 2022 at 2:32 PM Michal Simek <michal.si...@xilinx.com> wrote: > >> > >> > >> > >> On 6/1/22 10:46, Oleksandr Suvorov wrote: > >>> Store a set of supported bitstream types in xilinx_desc structure. > >>> It will be used to determine whether an FPGA image is able to be > >>> loaded with a given driver. > >>> > >>> Signed-off-by: Oleksandr Suvorov <oleksandr.suvo...@foundries.io> > >>> --- > >>> > >>> (no changes since v1) > >>> > >>> include/versalpl.h | 2 +- > >>> include/xilinx.h | 5 +++++ > >>> include/zynqmppl.h | 2 +- > >>> 3 files changed, 7 insertions(+), 2 deletions(-) > >>> > >>> diff --git a/include/versalpl.h b/include/versalpl.h > >>> index b94c82e6e66..26f04a2f649 100644 > >>> --- a/include/versalpl.h > >>> +++ b/include/versalpl.h > >>> @@ -15,6 +15,6 @@ > >>> extern struct xilinx_fpga_op versal_op; > >>> > >>> #define XILINX_VERSAL_DESC \ > >>> -{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op } > >>> +{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL, > >>> FPGA_LEGACY } > >>> > >>> #endif /* _VERSALPL_H_ */ > >>> diff --git a/include/xilinx.h b/include/xilinx.h > >>> index 362943bc717..91179abe31f 100644 > >>> --- a/include/xilinx.h > >>> +++ b/include/xilinx.h > >>> @@ -37,6 +37,9 @@ typedef enum { /* typedef > >>> xilinx_family */ > >>> max_xilinx_type /* insert all new types before this */ > >>> } xilinx_family; /* end, typedef xilinx_family */ > >>> > >>> +/* FPGA bitstream supported types */ > >>> +#define FPGA_LEGACY BIT(0) > >>> + > >>> typedef struct { /* typedef xilinx_desc */ > >>> xilinx_family family; /* part type */ > >>> xilinx_iface iface; /* interface type */ > >>> @@ -45,6 +48,7 @@ typedef struct { /* typedef xilinx_desc */ > >>> int cookie; /* implementation specific cookie */ > >>> struct xilinx_fpga_op *operations; /* operations */ > >>> char *name; /* device name in bitstream */ > >>> + int flags; /* compatible flags */ > >>> } xilinx_desc; /* end, typedef xilinx_desc */ > >>> > >>> struct xilinx_fpga_op { > >>> @@ -56,6 +60,7 @@ struct xilinx_fpga_op { > >>> struct fpga_secure_info *fpga_sec_info); > >>> int (*dump)(xilinx_desc *desc, const void *buf, size_t bsize); > >>> int (*info)(xilinx_desc *desc); > >>> + int (*str2flag)(xilinx_desc *desc, const char *string); > >> > >> This should be in 4/13. > >> > >> M > > > > Thanks, Michal! Agree. I'll post the fixed patchset after receiving > > the testing feedback from Ricardo and Adrian. > > ok. I think series in general going in right direction based on current fpga > framework style. Would be better to move it to DM but none is pushing you to > do it.
Yeah, I started adding the DM version, but it needs way extra time, I'm not sure I'll be able to complete it even in a month (not enough free time for that). > What needs to be fixed are that return values where flags and fpga status > values > are mixed together. And making sure that secure options are available only > when > secure configuration is enabled. Ok, thanks, I'll revise these points. > > Thanks, > Michal -- Best regards Oleksandr Oleksandr Suvorov cryo...@gmail.com