On Tue, May 17, 2022 at 05:41:39PM +0900, Masahisa Kojima wrote: > There is a TX-FIFO and Shift Register empty(TFES) status > bit in spi controller. This commit checks the TFES bit > to wait the TX transfer completes. > > Signed-off-by: Masahisa Kojima <masahisa.koj...@linaro.org> > Signed-off-by: Satoru Okamoto <okamoto.sat...@socionext.com> > Acked-by: Jassi Brar <jaswinder.si...@linaro.org>
Applied to u-boot/next, thanks! -- Tom
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