On Tue, Jun 21, 2022 at 04:36:03PM -0500, Bryan Brattlof wrote: > Anytime a new revision of a chip is produced, Texas Instruments > will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID > register by one. Typically this will be decoded as SR1.0 -> SR2.0 ... > however a few TI SoCs do not follow this convention. > > Rather than defining a revision string array for each SoC, use a > default revision string array for all TI SoCs that continue to follow > the typical 1.0 -> 2.0 revision scheme. > > Signed-off-by: Bryan Brattlof <b...@ti.com>
Applied to u-boot/next, thanks! -- Tom
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