On Tue, Aug 30, 2022 at 9:34 AM Marek Vasut <[email protected]> wrote: > > Adjust the DRAM timing settings for this board per ones provided > by hardware department. The change is applied to the LPDDR4 MR11 > register CA ODT configuration, from RZQ/6 to RZQ/3, which fixes > stability issues on subset of boards. The DDR PHY PIE block has > been updated accordingly. > > Signed-off-by: Marek Vasut <[email protected]> > Cc: Fabio Estevam <[email protected]> > Cc: Peng Fan <[email protected]> > Cc: Stefano Babic <[email protected]>
Looks like this one should be applied to 2022.10: Reviewed-by: Fabio Estevam <[email protected]>
