> From: Heinrich Schuchardt <[email protected]> > Sent: Sunday, October 02, 2022 10:21 AM > To: Tom Rini <[email protected]>; Leo Yu-Chi Liang(梁育齊) > <[email protected]>; Rick Jian-Zhi Chen(陳建志) <[email protected]>; Simon > Glass <[email protected]> > Cc: [email protected]; Alexandre Ghiti <[email protected]>; > Aurelien Jarno <[email protected]>; Bin Meng <[email protected]>; > Heinrich Schuchardt <[email protected]>; Heiko Stuebner > <[email protected]>; Christian Stewart <[email protected]> > Subject: [PATCH v3 3/3] riscv: Fix build against binutils 2.38 > > From: Alexandre Ghiti <[email protected]> > > The following description is copied from the equivalent patch for the Linux > Kernel proposed by Aurelien Jarno: > > >From version 2.38, binutils default to ISA spec version 20191213. This > means that the csr read/write (csrr*/csrw*) instructions and fence.i > instruction has separated from the `I` extension, become two standalone > extensions: Zicsr and Zifencei. As the kernel uses those instruction, this > causes the following build failure: > > arch/riscv/cpu/mtrap.S: Assembler messages: > arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' > arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' > arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' > arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' > > Signed-off-by: Alexandre Ghiti <[email protected]> > Reviewed-by: Bin Meng <[email protected]> > Tested-by: Heinrich Schuchardt <[email protected]> > Tested-by: Heiko Stuebner <[email protected]> > Tested-by: Christian Stewart <[email protected]> > --- > v3: > no change > --- > arch/riscv/Makefile | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen <[email protected]>
