> From: Yanhong Wang <yanhong.w...@starfivetech.com> > Sent: Monday, December 12, 2022 10:50 AM > To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志) <r...@andestech.com>; Leo > Yu-Chi Liang(梁育齊) <ycli...@andestech.com>; Lukasz Majewski <lu...@denx.de>; > Sean Anderson <sean...@gmail.com> > Cc: Lee Kuan Lim <kuanlim....@starfivetech.com>; Jianlong Huang > <jianlong.hu...@starfivetech.com>; Emil Renner Berthing <ker...@esmil.dk>; > Yanhong Wang <yanhong.w...@starfivetech.com> > Subject: [PATCH v1 01/17] riscv: cpu: jh7110: Add support for jh7110 SoC > > Add StarFive JH7110 SoC to support RISC-V arch. > > Signed-off-by: Yanhong Wang <yanhong.w...@starfivetech.com> > --- > arch/riscv/cpu/jh7110/Makefile | 10 ++++ > arch/riscv/cpu/jh7110/cpu.c | 23 ++++++++ > arch/riscv/cpu/jh7110/dram.c | 38 +++++++++++++ > arch/riscv/cpu/jh7110/spl.c | 56 +++++++++++++++++++ > .../include/asm/arch-jh7110/jh7110-regs.h | 20 +++++++ > arch/riscv/include/asm/arch-jh7110/spl.h | 13 +++++ > 6 files changed, 160 insertions(+)
Reviewed-by: Rick Chen <r...@andestech.com>
