On T30 unlike T20 dsi panels are wider used on devices so PLLD is used as DISP1 parent more often, so lets enable it as well for this cases.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF700T T30 Tested-by: Svyatoslav Ryhel <[email protected]> # HTC One X T30 Signed-off-by: Svyatoslav Ryhel <[email protected]> --- arch/arm/mach-tegra/clock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 7eada78d3a..95cc48888c 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -791,16 +791,19 @@ void tegra30_set_up_pllp(void) case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 456, 12, 1, 8); break; case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 600, 26, 0, 8); break; case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 600, 13, 0, 8); break; case CLOCK_OSC_FREQ_19_2: default: -- 2.37.2
