> From: Peter Yu-Chien Lin(林宇謙) <peter...@andestech.com>
> Sent: Thursday, January 19, 2023 3:06 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) <ycli...@andestech.com>; Rick Jian-Zhi Chen(陳建志)
> <r...@andestech.com>; Peter Yu-Chien Lin(林宇謙) <peter...@andestech.com>
> Subject: [PATCH 01/11] riscv: global_data.h: Correct the comment for PLICSW
>
> PLIC is used for external interrupt, while PLICSW is an Andes-specific design
> for software interrupt.
>
> Signed-off-by: Yu Chien Peter Lin <peter...@andestech.com>
> ---
> arch/riscv/include/asm/global_data.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
It seems not relative to cache.
Other than that,
Reviewed-by: Rick Chen <r...@andestech.com>
>
> diff --git a/arch/riscv/include/asm/global_data.h
> b/arch/riscv/include/asm/global_data.h
> index 6fdc86dd8b..31ba72693d 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -22,7 +22,7 @@ struct arch_global_data {
> void __iomem *clint; /* clint base address */
> #endif
> #ifdef CONFIG_ANDES_PLICSW
> - void __iomem *plicsw; /* plic base address */
> + void __iomem *plicsw; /* andes plicsw base address */
> #endif
> #if CONFIG_IS_ENABLED(SMP)
> struct ipi_data ipi[CONFIG_NR_CPUS];
> --
> 2.34.1
