> Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency > restrictions. Detail clock rate changes in the patch: > PLL3 PFD2: 389M -> 324M > PLL3 PFD3: 336M -> 389M > PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD) > PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD) > PLL4 PFD0: 792M -> 594M > PLL4 PFD2: 792M -> 316.8M > NIC_AP: 96M (ND) -> 192M, 48M (LD) -> 96M > NIC_LPAV: 198 (ND) -> 192M, 99M (LD) -> 96M > USDHC0: PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD) > USDHC1: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) > USDHC2: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) > Signed-off-by: Ye Li <[email protected]> > Reviewed-by: Peng Fan <[email protected]> Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: [email protected] =====================================================================
