> At present, in cgc1_pll3_init we don't set the pll3pfd div values, > just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2 > to 1 and pfd2div1 to 3. > This finally causes some clocks' rate decreased, for example USDHC. > So clear the PLL3DIV_PFD dividers to get correct rate. > Signed-off-by: Ye Li <[email protected]> > Reviewed-by: Peng Fan <[email protected]> Applied to u-boot-imx, -next, thanks !
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