On 2023/4/26 23:53, Eugen Hristev wrote:
From: Jon Lin <[email protected]> Add support for max_link_speed specified in the PCI DT binding. Signed-off-by: Jon Lin <[email protected]> [[email protected]: port to latest API, set default correctly, align to 80 chars] Signed-off-by: Eugen Hristev <[email protected]> [[email protected]: switch to dev_read_u32_default] Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]> Thanks, - Kever
--- Changes in v2: - move to dev_read_u32_default drivers/pci/pcie_dw_rockchip.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index ff121046604a..60c74bea24b2 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -42,6 +42,7 @@ struct rk_pcie { struct clk_bulk clks; struct reset_ctl_bulk rsts; struct gpio_desc rst_gpio; + u32 gen; };/* Parameters for the waiting for iATU enabled routine */@@ -331,7 +332,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) rk_pcie_writel_apb(priv, 0x0, 0xf00040); pcie_dw_setup_host(&priv->dw);- ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3);+ ret = rk_pcie_link_up(priv, priv->gen); if (ret < 0) goto err_link_up;@@ -397,6 +398,9 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)goto rockchip_pcie_parse_dt_err_phy_get_by_index; }+ priv->gen = dev_read_u32_default(dev, "max-link-speed",+ LINK_SPEED_GEN_3); + return 0;rockchip_pcie_parse_dt_err_phy_get_by_index:
