On 2023/4/22 09:23, Jonas Karlman wrote:
Update defconfig for rk3588-rock-5b with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>

Thanks,
- Kever
---
  configs/rock5b-rk3588_defconfig | 7 +++----
  1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 2e034b724cc9..2f0a74ee5559 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
  CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
  CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
  CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_SPL_MMC=y
  CONFIG_SPL_SERIAL=y
  CONFIG_SPL_STACK_R_ADDR=0x600000
  CONFIG_TARGET_ROCK5B_RK3588=y
@@ -29,7 +27,7 @@ CONFIG_OF_BOARD_SETUP=y
  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
  # CONFIG_DISPLAY_CPUINFO is not set
  CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_MAX_SIZE=0x40000
  CONFIG_SPL_PAD_TO=0x7f8000
  CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
  CONFIG_SPL_BSS_START_ADDR=0x4000000
@@ -38,6 +36,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
  # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
  CONFIG_SPL_STACK_R=y
  CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
  CONFIG_CMD_GPT=y
  CONFIG_CMD_MMC=y
  CONFIG_CMD_USB=y
@@ -47,7 +46,6 @@ CONFIG_CMD_REGULATOR=y
  CONFIG_SPL_OF_CONTROL=y
  CONFIG_OF_LIVE=y
  CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
-CONFIG_NET_RANDOM_ETHADDR=y
  CONFIG_SPL_REGMAP=y
  CONFIG_SPL_SYSCON=y
  CONFIG_SPL_CLK=y
@@ -70,6 +68,7 @@ CONFIG_PWM_ROCKCHIP=y
  CONFIG_SPL_RAM=y
  CONFIG_BAUDRATE=1500000
  CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
  CONFIG_SYSRESET=y
  CONFIG_USB=y
  CONFIG_USB_EHCI_HCD=y

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