Hi Bhavya!
On May 11, 2023 thus sayeth Bhavya Kapoor:
> Add main_uart5 clocks in clk-data.c for J721S2. Now,
> main_uart5 clocks will be set up while booting the J721S2 SoC.
>
> Signed-off-by: Bhavya Kapoor <b-kap...@ti.com>
> ---
> arch/arm/mach-k3/j721s2/clk-data.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-k3/j721s2/clk-data.c
> b/arch/arm/mach-k3/j721s2/clk-data.c
> index ad6bd991b7..0c5c321c1e 100644
> --- a/arch/arm/mach-k3/j721s2/clk-data.c
> +++ b/arch/arm/mach-k3/j721s2/clk-data.c
> @@ -247,6 +247,7 @@ static const struct clk_data clk_list[] = {
> CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2,
> 0x1080b4, 16, 1, 0),
> CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2,
> 0x40f08010, 0, 1, 0),
> CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0",
> "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
> + CLK_DIV("usart_programmable_clock_divider_out5",
> "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
Is this being used as an alternate console? idk if it would be
appropriate to use CLK_DIV_DEFFREQ macro here to setup the uart's
divider here.
~Bryan
