Add dummy support for the CLK_PCIEPHY2_REF clock.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
---
v2:
- Collect r-b tag
drivers/clk/rockchip/clk_rk3568.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk_rk3568.c
b/drivers/clk/rockchip/clk_rk3568.c
index 6bdd96f35b5c..0df82f597152 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong
rate)
break;
case CLK_PCIEPHY0_REF:
case CLK_PCIEPHY1_REF:
+ case CLK_PCIEPHY2_REF:
return 0;
default:
return -ENOENT;
--
2.40.1
