On 5/17/23 11:41 PM, Yanhong Wang wrote:
SPL runs on the L2 LIM, which is 2M in size mapped at 0x8000000.This
region consists of 16 0x20000 sized regions, each one can be used as
either L2 cache way or SRAM (not both).From top to bottom, you have way
0-15.The way 0 is always enabled, so SPL can only use at most 0x1e0000
bytes of memory.So, update the value of the CONFIG_SPL_STACK to
0x81CFFFF.
Signed-off-by: Yanhong Wang <[email protected]>
---
configs/starfive_visionfive2_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index ffbc4b9476..fc3d27bbec 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -13,7 +13,7 @@ CONFIG_SYS_PROMPT="StarFive #"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
-CONFIG_SPL_STACK=0x8180000
+CONFIG_SPL_STACK=0x81CFFFF
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
Hi Yanhong, Thanks for taking care of this. Would you mind refer my
name if you want to directly copy-paste my previous response?
(https://lists.denx.de/pipermail/u-boot/2023-May/518359.html)
Regarding the patch itself, I don't quite understand it. If you want
to fully utilize the L2 LIM, then we should have CONFIG_SPL_STACK=0x81e0000.
Let me know if I missed anything. Thanks.
