From: Dhananjay Kangude <[email protected]>

Renaming the functions and structures specific to SD4 so
that it can be separated from upcoming SD6 related
functionality.

Signed-off-by: Dhananjay Kangude <[email protected]>
Co-developed-by: Jayanthi Annadurai <[email protected]>
Signed-off-by: Jayanthi Annadurai <[email protected]>
Signed-off-by: Piyush Malgujar <[email protected]>
---
 drivers/mmc/sdhci-cadence.c | 48 ++++++++++++++++++-------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
index 
327a05ad11d00fad415bd18b93d83f08e2b6ed5a..0bb258da63e442232310d9433b7b6882992bd45d
 100644
--- a/drivers/mmc/sdhci-cadence.c
+++ b/drivers/mmc/sdhci-cadence.c
@@ -18,14 +18,14 @@
 #include <mmc.h>
 #include <sdhci.h>
 
-/* HRS - Host Register Set (specific to Cadence) */
+/* SD 4.0 Controller HRS - Host Register Set (specific to Cadence) */
 #define SDHCI_CDNS_HRS04               0x10            /* PHY access port */
-#define   SDHCI_CDNS_HRS04_ACK                 BIT(26)
-#define   SDHCI_CDNS_HRS04_RD                  BIT(25)
-#define   SDHCI_CDNS_HRS04_WR                  BIT(24)
-#define   SDHCI_CDNS_HRS04_RDATA               GENMASK(23, 16)
-#define   SDHCI_CDNS_HRS04_WDATA               GENMASK(15, 8)
-#define   SDHCI_CDNS_HRS04_ADDR                        GENMASK(5, 0)
+#define SDHCI_CDNS_SD4_HRS04_ACK               BIT(26)
+#define SDHCI_CDNS_SD4_HRS04_RD                        BIT(25)
+#define SDHCI_CDNS_SD4_HRS04_WR                        BIT(24)
+#define SDHCI_CDNS_SD4_HRS04_RDATA             GENMASK(23, 16)
+#define SDHCI_CDNS_SD4_HRS04_WDATA             GENMASK(15, 8)
+#define SDHCI_CDNS_SD4_HRS04_ADDR              GENMASK(5, 0)
 
 #define SDHCI_CDNS_HRS06               0x18            /* eMMC control */
 #define   SDHCI_CDNS_HRS06_TUNE_UP             BIT(15)
@@ -41,7 +41,7 @@
 /* SRS - Slot Register Set (SDHCI-compatible) */
 #define SDHCI_CDNS_SRS_BASE            0x200
 
-/* PHY */
+/* PHY registers for SD4 controller */
 #define SDHCI_CDNS_PHY_DLY_SD_HS       0x00
 #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT  0x01
 #define SDHCI_CDNS_PHY_DLY_UHS_SDR12   0x02
@@ -73,7 +73,7 @@ struct sdhci_cdns_phy_cfg {
        u8 addr;
 };
 
-static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
+static const struct sdhci_cdns_phy_cfg sdhci_cdns_sd4_phy_cfgs[] = {
        { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
        { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
        { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
@@ -87,45 +87,45 @@ static const struct sdhci_cdns_phy_cfg 
sdhci_cdns_phy_cfgs[] = {
        { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
 };
 
-static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
-                                   u8 addr, u8 data)
+static int sdhci_cdns_sd4_write_phy_reg(struct sdhci_cdns_plat *plat,
+                                       u8 addr, u8 data)
 {
        void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
        u32 tmp;
        int ret;
 
-       tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
-             FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
+       tmp = FIELD_PREP(SDHCI_CDNS_SD4_HRS04_WDATA, data) |
+               FIELD_PREP(SDHCI_CDNS_SD4_HRS04_ADDR, addr);
        writel(tmp, reg);
 
-       tmp |= SDHCI_CDNS_HRS04_WR;
+       tmp |= SDHCI_CDNS_SD4_HRS04_WR;
        writel(tmp, reg);
 
-       ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
+       ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_SD4_HRS04_ACK, 10);
        if (ret)
                return ret;
 
-       tmp &= ~SDHCI_CDNS_HRS04_WR;
+       tmp &= ~SDHCI_CDNS_SD4_HRS04_WR;
        writel(tmp, reg);
 
        return 0;
 }
 
-static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
-                               const void *fdt, int nodeoffset)
+static int sdhci_cdns_sd4_phy_init(struct sdhci_cdns_plat *plat,
+                                  const void *fdt, int nodeoffset)
 {
        const fdt32_t *prop;
        int ret, i;
 
-       for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
+       for (i = 0; i < ARRAY_SIZE(sdhci_cdns_sd4_phy_cfgs); i++) {
                prop = fdt_getprop(fdt, nodeoffset,
-                                  sdhci_cdns_phy_cfgs[i].property, NULL);
+                               sdhci_cdns_sd4_phy_cfgs[i].property, NULL);
                if (!prop)
                        continue;
 
-               ret = sdhci_cdns_write_phy_reg(plat,
-                                              sdhci_cdns_phy_cfgs[i].addr,
-                                              fdt32_to_cpu(*prop));
+               ret = sdhci_cdns_sd4_write_phy_reg(plat,
+                                                  
sdhci_cdns_sd4_phy_cfgs[i].addr,
+                                                  fdt32_to_cpu(*prop));
                if (ret)
                        return ret;
        }
@@ -282,7 +282,7 @@ static int sdhci_cdns_probe(struct udevice *dev)
        if (ret)
                return ret;
 
-       ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
+       ret = sdhci_cdns_sd4_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
        if (ret)
                return ret;
 
-- 
2.17.1

Reply via email to