> From: Bin Meng <[email protected]> > Sent: Monday, June 12, 2023 3:36 PM > To: [email protected] > Cc: Andre Przywara <[email protected]>; Anup Patel > <[email protected]>; Jonas Schwöbel <[email protected]>; Kautuk > Consul <[email protected]>; Leo Yu-Chi Liang(梁育齊) > <[email protected]>; Michael Walle <[email protected]>; Michal Simek > <[email protected]>; Nikita Shubin <[email protected]>; Rick Jian-Zhi > Chen(陳建志) <[email protected]>; Sean Anderson <[email protected]>; Sergei > Antonov <[email protected]>; Simon Glass <[email protected]>; Stefan > Herbrechtsmeier <[email protected]>; Svyatoslav Ryhel > <[email protected]>; Tianrui Wei <[email protected]>; William Zhang > <[email protected]>; Yanhong Wang <[email protected]>; > Peter Yu-Chien Lin(林宇謙) <[email protected]> > Subject: [PATCH 3/3] riscv: Rename SiFive CLINT to RISC-V ALINT > > As the RISC-V ACLINT specification is defined to be backward compatible with > the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the > source tree to be future-proof. > > Signed-off-by: Bin Meng <[email protected]> > > --- > > MAINTAINERS | 2 +- > arch/riscv/Kconfig | 8 ++++---- > arch/riscv/cpu/fu540/Kconfig | 2 +- > arch/riscv/cpu/fu740/Kconfig | 2 +- > arch/riscv/cpu/generic/Kconfig | 4 ++-- > arch/riscv/cpu/jh7110/Kconfig | 2 +- > arch/riscv/include/asm/global_data.h | 4 ++-- > arch/riscv/include/asm/syscon.h | 2 +- > arch/riscv/lib/Makefile | 2 +- > .../lib/{sifive_clint.c => aclint_ipi.c} | 16 +++++++-------- > board/openpiton/riscv64/Kconfig | 2 +- > board/sipeed/maix/Kconfig | 2 +- > drivers/timer/Makefile | 2 +- > ...ive_clint_timer.c => riscv_aclint_timer.c} | 20 +++++++++---------- > 14 files changed, 35 insertions(+), 35 deletions(-) rename > arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (73%) rename > drivers/timer/{sifive_clint_timer.c => riscv_aclint_timer.c} (75%)
Reviewed-by: Rick Chen <[email protected]>
